drivers: flash: flash_stm32_qspi: Make CS high time configurable #92742
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The QSPI 1/2 sample shift (SSHIFT) was only enabled in dual flash mode. This feature is useful to guarantee that data is ready at the sampling moment, even if the signals are a bit delayed due to PCB constraints. Therefore, it should be enabled when possible (only supported in STR mode). Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
The STM32 QUADSPI peripheral allows to configure, in clock cycles, the duration the chip select signal must stay high between each command sent to the flash memory controller (QUADSPI_DCR_CSHT). Currently, this value is set by the flash driver to 1 clock cycle in single flash mode and 3 clock cycles in dual flash mode. However, the minimal duration depends on the flash memory (typically 30-50 ns) and the number of clock cycles on the QSPI's clock frequency. So, adding this new property allows to select the value of CSHT to match the requirement of the flash memory used. Also note that in single flash mode, the current configuration is out-of-spec for most flash memories. A default value of 4 clock cycles is used. This is enough for all board configurations currently provided by Zephyr (flash memory needing up 50 ns and frequency up to 80 MHz). Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
This commit set the value of the cs-high-time property for all STM32-based boards defined in Zephyr and having a QSPI flash memory. The value is chosen according to the flash memory requirements (often named 'tSHSL' in the datasheets) and the maximum QSPI frequency. Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
This commit adds support for the new cs-high-time devicetree property. The QUADSPI_DCR_CSHT is now configured according to the value indicated in the devicetree, for both single and dual flash modes. Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
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The STM32 QUADSPI peripheral allows to configure, in clock cycles, the duration the chip select signal must stay high between each command sent to the flash memory controller (
QUADSPI_DCR_CSHT).This value should be configured according to:
Currently, this value is set by the flash driver to 1 clock cycle in single flash mode and 3 clock cycles in dual flash mode. This may be too low for some configurations. In particular, in single flash mode, the current value is out-of-spec for all board configurations provided by Zephyr.
This MR adds a new devicetree property allowing to set the chip-select high time value according to the flash memory specifications and the QSPI configuration.
Secondarily, this MR also enables the 1/2 sample shift feature of the QUADSPI peripheral in both single and dual flash mode.
From RM0433:
From MT25QL512 datasheet (used on the STM32H747I-DISCO board):
