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drivers: flash: flash_stm32_qspi: Make CS high time configurable #92742

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drivers: flash: flash_stm32_qspi: Make CS high time configurable #92742

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90751c4
drivers: flash: stm32_qspi: Use sample shift also in single flash mode
taltenbach Jul 5, 2025
0566242
dts: bindings: flash_controller: Add CS high time to stm32-qspi-nor
taltenbach Jul 5, 2025
8de251d
boards: Add cs-high-time for all STM32 boards using QSPI flash
taltenbach Jul 5, 2025
e3e71db
drivers: flash: flash_stm32_qspi: Add support for cs-high-time
taltenbach Jul 5, 2025
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1 change: 1 addition & 0 deletions boards/alientek/pandora_stm32l475/pandora_stm32l475.dts
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Expand Up @@ -82,6 +82,7 @@
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <80000000>;
cs-high-time = <4>; /* >= 50 ns */
jedec-id = [ef 40 18];
spi-bus-width = <4>;
writeoc = "PP_1_1_4";
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1 change: 1 addition & 0 deletions boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts
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Expand Up @@ -178,6 +178,7 @@
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
status = "okay";

partitions {
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1 change: 1 addition & 0 deletions boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts
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Expand Up @@ -170,6 +170,7 @@ zephyr_i2c: &i2c1 {
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
status = "okay";

partitions {
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1 change: 1 addition & 0 deletions boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi
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Expand Up @@ -184,6 +184,7 @@ zephyr_i2c: &i2c1 {
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = < 40000000 >;
cs-high-time = <2>; /* >= 30 ns */
sfdp-bfp = [ e5 20 f1 ff ff ff ff 07 44 eb 08 6b 08 3b 04 bb
fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52
10 d8 00 ff 82 41 bd 00 81 e5 7b c6 44 03 67 38
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1 change: 1 addition & 0 deletions boards/fanke/fk743m5_xih6/fk743m5_xih6.dts
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Expand Up @@ -101,6 +101,7 @@
reg = <0>;
size = <DT_SIZE_M(64)>; /* 64 Mbits */
qspi-max-frequency = <40000000>;
cs-high-time = <2>; /* >= 50 ns */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_1_4";
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1 change: 1 addition & 0 deletions boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts
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Expand Up @@ -123,6 +123,7 @@
reg = <0>;
size = <DT_SIZE_M(64)>; /* 64 Mbits */
qspi-max-frequency = <40000000>;
cs-high-time = <2>; /* >= 50 ns */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_1_4";
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1 change: 1 addition & 0 deletions boards/st/disco_l475_iot1/disco_l475_iot1.dts
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Expand Up @@ -330,6 +330,7 @@ zephyr_udc0: &usbotg_fs {
reg = <0>;
size = <DT_SIZE_M(64)>; /* 64 Mbits */
qspi-max-frequency = <50000000>;
cs-high-time = <2>; /* >= 30 ns */
status = "okay";

partitions {
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1 change: 1 addition & 0 deletions boards/st/stm32f412g_disco/stm32f412g_disco.dts
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Expand Up @@ -161,6 +161,7 @@
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
status = "okay";
};
};
1 change: 1 addition & 0 deletions boards/st/stm32f723e_disco/stm32f723e_disco.dts
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Expand Up @@ -132,6 +132,7 @@
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
qspi-max-frequency = <8000000>;
cs-high-time = <3>; /* >= 30 ns */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_4_4";
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1 change: 1 addition & 0 deletions boards/st/stm32f746g_disco/stm32f746g_disco.dts
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Expand Up @@ -215,6 +215,7 @@ zephyr_udc0: &usbotg_fs {
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
status = "okay";

partitions {
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1 change: 1 addition & 0 deletions boards/st/stm32f7508_dk/stm32f7508_dk.dts
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Expand Up @@ -202,6 +202,7 @@ zephyr_udc0: &usbotg_fs {
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
status = "okay";

partitions {
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1 change: 1 addition & 0 deletions boards/st/stm32f769i_disco/stm32f769i_disco.dts
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Expand Up @@ -200,6 +200,7 @@ arduino_serial: &usart6 {};
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
qspi-max-frequency = <DT_FREQ_M(66)>;
cs-high-time = <2>; /* >= 30 ns */
status = "okay";

partitions {
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1 change: 1 addition & 0 deletions boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
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Expand Up @@ -185,6 +185,7 @@
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
spi-bus-width = <4>;
reset-cmd;
status = "okay";
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1 change: 1 addition & 0 deletions boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -258,6 +258,7 @@ zephyr_udc0: &usbotg_hs {
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
spi-bus-width = <4>;
reset-cmd;
status = "okay";
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1 change: 1 addition & 0 deletions boards/st/stm32h750b_dk/stm32h750b_dk.dts
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Expand Up @@ -192,6 +192,7 @@
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
spi-bus-width = <4>;
reset-cmd;
status = "okay";
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1 change: 1 addition & 0 deletions boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts
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Expand Up @@ -273,6 +273,7 @@ zephyr_udc0: &usbotg_hs {
reg = <0>;
size = <DT_SIZE_M(512)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
cs-high-time = <4>; /* >= 50 ns */
spi-bus-width = <4>;
reset-cmd;
status = "okay";
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1 change: 1 addition & 0 deletions boards/st/stm32l496g_disco/stm32l496g_disco.dts
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Expand Up @@ -211,6 +211,7 @@ zephyr_udc0: &usbotg_fs {
reg = <0>;
size = <DT_SIZE_M(64)>; /* 64 Mbits */
qspi-max-frequency = <8000000>;
cs-high-time = <3>; /* >= 30 ns */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_4_4";
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1 change: 1 addition & 0 deletions boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts
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Expand Up @@ -119,6 +119,7 @@
reg = <0>;
size = <DT_SIZE_M(128)>; /* 128 Mbits */
qspi-max-frequency = <80000000>;
cs-high-time = <4>; /* >= 50 ns */
spi-bus-width = <4>;
status = "okay";

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1 change: 1 addition & 0 deletions boards/weact/mini_stm32h743/mini_stm32h743.dts
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Expand Up @@ -171,6 +171,7 @@ zephyr_udc0: &usbotg_fs {
reg = <0>;
size = <DT_SIZE_M(64)>; /* 64 Mbits */
qspi-max-frequency = <40000000>;
cs-high-time = <2>; /* >= 50 ns */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_1_4";
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6 changes: 4 additions & 2 deletions drivers/flash/flash_stm32_qspi.c
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Expand Up @@ -102,6 +102,7 @@ struct flash_stm32_qspi_config {
irq_config_func_t irq_config;
size_t flash_size;
uint32_t max_frequency;
uint8_t cs_high_time;
const struct pinctrl_dev_config *pcfg;
#if STM32_QSPI_RESET_GPIO
const struct gpio_dt_spec reset;
Expand Down Expand Up @@ -1510,15 +1511,15 @@ static int flash_stm32_qspi_init(const struct device *dev)
dev_data->hqspi.Init.ClockPrescaler = prescaler;
/* Give a bit position from 0 to 31 to the HAL init minus 1 for the DCR1 reg */
dev_data->hqspi.Init.FlashSize = find_lsb_set(dev_cfg->flash_size) - 2;
dev_data->hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
dev_data->hqspi.Init.ChipSelectHighTime = dev_cfg->cs_high_time - 1;
#if DT_PROP(DT_NODELABEL(quadspi), dual_flash) && defined(QUADSPI_CR_DFM)
/*
* When the DTS has <dual-flash>, it means Dual Flash Mode
* Even in DUAL flash config, the SDFP is read from one single quad-NOR
* else the magic nb is wrong (0x46465353)
* That means that the Dual Flash config is set after the SFDP sequence
*/
dev_data->hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
dev_data->hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE;
dev_data->hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
/* Set Dual Flash Mode only on MemoryMapped */
dev_data->hqspi.Init.FlashID = QSPI_FLASH_ID_1;
Expand Down Expand Up @@ -1705,6 +1706,7 @@ static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = {
.irq_config = flash_stm32_qspi_irq_config_func,
.flash_size = (DT_INST_PROP(0, size) / 8) << STM32_QSPI_DOUBLE_FLASH,
.max_frequency = DT_INST_PROP(0, qspi_max_frequency),
.cs_high_time = DT_INST_PROP(0, cs_high_time),
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_QSPI_NODE),
#if STM32_QSPI_RESET_GPIO
.reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
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7 changes: 7 additions & 0 deletions dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
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Expand Up @@ -80,3 +80,10 @@ properties:
type: int
default: 8
description: The number of dummy-cycles required when reading jedec id

cs-high-time:
type: int
default: 4
description: |
Minimum number of QSPI clock cycles the chip select signal must remain
high between commands issued to the flash memory.
1 change: 1 addition & 0 deletions samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay
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Expand Up @@ -47,6 +47,7 @@
reg = <0>;
size = <DT_SIZE_M(256)>; /* 256 Mbits */
qspi-max-frequency = <50000000>;
cs-high-time = <3>; /* >= 30 ns */
reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
reset-gpios-duration = <1>;
spi-bus-width = <4>;
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