STM32L0: fix PLL input frequency division by HSI clock divider #92546
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| @@ -662,7 +662,13 @@ static void set_up_fixed_clock_sources(void) | |||
| } | |||
| } | |||
| #if STM32_HSI_DIV_ENABLED | |||
| #if defined(CONFIG_SOC_SERIES_STM32L0X) | |||
| if (LL_RCC_IsActiveFlag_HSIDIV()) { | |||
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I don't understand why this check is there.
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replaced with STM32_HSI_DIVISOR check.
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Add hsi clock for stm32l0. Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Enable support for HSI_DIV and its use as a clock source on STM32L0 SoCs. Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
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Updated the clk_hsi node to use the "st,stm32l0-hsi-clock" compatible to use hsi divider. Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Updated the PLL input frequency calculation to include division by the HSI clock divider. Enable HSI divider using LL_RCC_HSI_EnableDivider(). Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
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etienne-lms
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| if (STM32_HSI_DIVISOR == 4) { | ||
| LL_RCC_HSI_EnableDivider(); | ||
| } |
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The disable function should also be called in an else. I think it is necessary if for example an MCUBoot enables the divider, but the application wants it disabled
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In the STM32L0 clock driver the HSI clock divider is not considered when calculating the PLL source frequency (register value RCC_CR/HSIDIV).
Add new clocks bindings for stm32l0 series "st,stm32l0-hsi-clock" to use hsi-div property.
Updated the clk_hsi node to use the "st,stm32l0-hsi-clock" compatible to enable support for the HSI clock divider (hsi-div property).