drivers: clock_control: fix PLL input frequency

Updated the PLL input frequency calculation to include
division by the HSI clock divider.
Enable HSI divider using LL_RCC_HSI_EnableDivider().

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>

Author: kbidani

drivers/clock_control/clock_stm32_ll_common.c

@@ -662,7 +662,13 @@ static void set_up_fixed_clock_sources(void)
 			}
 		}
 #if STM32_HSI_DIV_ENABLED
+#if defined(CONFIG_SOC_SERIES_STM32L0X)
+		if (LL_RCC_IsActiveFlag_HSIDIV()) {
+			LL_RCC_HSI_EnableDivider();
+		}
+#else
 		LL_RCC_SetHSIDiv(hsi_divider(STM32_HSI_DIVISOR));
+#endif
 #endif
 	}
 

drivers/clock_control/clock_stm32l0_l1.c

@@ -49,7 +49,7 @@ __unused
 uint32_t get_pllsrc_frequency(void)
 {
 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
-		return STM32_HSI_FREQ;
+		return ((STM32_HSI_FREQ) / (STM32_HSI_DIVISOR));
 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
 		return STM32_HSE_FREQ;
 	}