Add minimal support for Renesas EK-RZ/A3M #91031

nhutnguyenkc · 2025-06-04T01:45:42Z

Add minimal support for EK-RZ/A3M as following:

Interface	Controller	Driver/Component
GPIO	on-chip	gpio
Pinctrl	on-chip	pinctrl
UART	on-chip	serial

Need: zephyrproject-rtos/hal_renesas#110
Doc: https://builds.zephyrproject.io/zephyr/pr/91031/docs/boards/renesas/rza3m_ek/doc/index.html

github-actions · 2025-06-04T01:47:17Z

The following west manifest projects have changed revision in this Pull Request:

Name	Old Revision	New Revision	Diff

✅ All manifest checks OK

Note: This message is automatically posted and updated by the Manifest GitHub Action.

khoa-nguyen-18 · 2025-06-04T06:39:32Z

boards/renesas/rza3m_ek/doc/index.rst

+  * R9A07G066M04GBG MPU
+  * 1GHz, Arm Cortex®-A55 core w/NEON extension
+  * Built-in 128MB DDR3L DRAM
+  * 128KB SRAM w/ECC


Since I see that the SRAM defined on the board layer is 72 KB, is this information correct?

Yes, SRAM is 128KB, but the first 56KB is reserved for bootloader, so only 72KB is available for use.

khoa-nguyen-18 · 2025-06-04T06:48:32Z

boards/renesas/rza3m_ek/rza3m_ek.dts

+	sram: memory@1e000 {
+		compatible ="zephyr,memory-region", "mmio-sram";
+		reg = <0x1e000 DT_SIZE_K(72)>;
+		zephyr,memory-region = "SRAM";
+	};


As I see in the HWM, this SRAM is in the SoC layer. Is there a specific reason for this node being placed here, or is my information incorrect?

SRAM is 128KB, but the first 56KB is reserved for bootloader, so only 72KB is available for use. The start address depends on the bootloader, so it has been moved to board layer.

khoa-nguyen-18 · 2025-06-04T06:56:14Z

soc/renesas/rz/rza3m/Kconfig.defconfig

+	default 512
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 24000000


Since the CPU frequency you defined is 1 GHz, this number doesn't match. Should we retrieve this value from the device tree instead of using a fixed value?

as above, get this value from dts using dts functions

Thanks. The generic timer is supplied by osc (24MHz). I added a node in dts and modify to get it. Please help me check again.

I think SYS_CLOCK_HW_CYCLES_PER_SEC should be assigned the value of the CPU clock, not the osc or any source of the CPU clock. In this case, I believe it would be the IΦ (CA55_SCLK) clock.

Thanks. But CA55_SCLK clock is totally wrong. Could you please refer to chapter 15 for system counter clock used as os timer?

khoa-nguyen-18 · 2025-06-04T06:58:32Z

tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.overlay

+&gpio {
+	status = "okay";
+};


Since the board has this node enabled, there's no need to overlay it in test.

I removed this node. Thanks

nordicjm · 2025-06-04T07:48:54Z

soc/renesas/rz/rza3m/Kconfig.defconfig

+	default 512
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 24000000


as above, get this value from dts using dts functions

boards/renesas/rza3m_ek/doc/rza3m_ek.webp

nordicjm · 2025-06-04T07:51:07Z

boards/renesas/rza3m_ek/rza3m_ek.dts

+			header: partition@0 {
+				label = "header";
+				reg = <0x00000000 0x200>;
+				read-only;
+			};


is this for mcuboot? If so, this is not correct. If it's something else then disregard

No, it isn't. An existing bootloader (pre-built binary) requires the header in a specific format to load the Zephyr image.

hmm is that without blobs? Boards in zephyr must be able to run samples without usage of binary blobs to be accepted - see https://docs.zephyrproject.org/latest/contribute/bin_blobs.html#limited-scope for details

Could you please help me check the html doc? We document it to guide users how to prepare the board including the bootloader.
https://builds.zephyrproject.io/zephyr/pr/91031/docs/boards/renesas/rza3m_ek/doc/index.html#programming-and-debugging

it's not about preparing, either those 2 samples work as-is without blobs or the board cannot be accepted into zephyr, if you need a binary blob IPL to run any application then the test cannot be passed under the without blobs requirement

Hi @nordicjm, @nashif, @kartben,
As the document https://docs.zephyrproject.org/latest/contribute/guidelines.html#licensing, the other licenses are also accepted (BSD 3-clause included), not only Apache 2.0

Also in the manifest of other vendors, they also use BSD 3-clause.
Example: https://github.com/zephyrproject-rtos/hal_nordic/blob/master/drivers/nrf_802154/driver/src/nrf_802154.c

I just reviewed the Zephyr policy regarding external source code integration:
https://docs.zephyrproject.org/latest/contribute/external.html#submission-and-review-process
As my understanding that https://github.com/renesas/hal_renesas has already been approved by the TSC.
Do I need to request TSC approval again for adding the IPL source code to hal_renesas?

Hi @nordicjm
Apologies if my earlier message came across too direct. I really appreciate the discussion and your support in helping us navigate this properly.

@nashif @kartben ping - assume needs discussing at TSC

@nordicjm Apache 2.0 requirement only applies to zephyr mainline, not modules. Modules when approved and created, document used license which needs to be compatible. Any new additions to the module/HAL under this license falls under the same approval. So, just because something else under that same approved license is being added to a module does not require TSC approval.

Are we including what is required to build even e.g. hello_world on board targets with that? ~~The original hal request was for apache 2.0 license #33171 so would not apply since this is for BSD licensed code~~ was a different PR for it which listed it #46721

fabiobaltieri · 2025-06-04T14:38:44Z

Hey, this needs a rebase and force push to pick up the CI error workaround.

kartben · 2025-06-27T13:45:20Z

@nhutnguyenkc CI is failing and this needs a rebase -- just a reminder that feature freeze is today :)

Add support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

Add devicetree to support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

This adds minimal support for board RZ/A3M-EK Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

Add pinctrl support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

Add GPIO driver support for RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

Exclude EK-RZ/A3M board as the redefined CONFIG_SRAM_BASE_ADDRESS degrades the BUILD_OUTPUT_ADJUST_LMA option that will generate a bin file >10GB Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

nhutnguyenkc · 2025-06-30T02:58:39Z

@kartben due to an issue, it has been moved to v4.3.0. I updated the milestone.

sonarqubecloud · 2025-06-30T03:06:19Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

github-actions bot added manifest manifest-hal_renesas labels Jun 4, 2025

nhutnguyenkc marked this pull request as ready for review June 4, 2025 03:16

github-actions bot added area: Pinctrl area: GPIO area: ARM64 ARM (64-bit) Architecture platform: Renesas R-Car Renesas R-Car platforms: Renesas RZ labels Jun 4, 2025

github-actions bot requested review from aaillet, binhnguyen2434, carlocaione, gmarull, henrikbrixandersen, ithinuel, JiafeiPan, lorc, mnkp, npitre, povergoing, SgrrZhf, tgorochowik, wearyzen and xakep-amatop June 4, 2025 03:18

github-actions bot assigned carlocaione Jun 4, 2025

nhutnguyenkc assigned binhnguyen2434 Jun 4, 2025

khoa-nguyen-18 reviewed Jun 4, 2025

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nordicjm requested changes Jun 4, 2025

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nhutnguyenkc force-pushed the rza3m_minimal_support branch from f75181f to 6f7fa44 Compare June 11, 2025 06:35

nhutnguyenkc force-pushed the rza3m_minimal_support branch 3 times, most recently from 6d8fae3 to fc5f9a0 Compare June 17, 2025 06:23

nhutnguyenkc force-pushed the rza3m_minimal_support branch from fc5f9a0 to bff6cd0 Compare June 19, 2025 10:34

github-actions bot added manifest manifest-hal_renesas DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Jun 19, 2025

KhiemNguyenT added this to the v4.2.0 milestone Jun 25, 2025

nordicjm previously approved these changes Jun 26, 2025

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binhnguyen2434 previously approved these changes Jun 26, 2025

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khoa-nguyen-18 approved these changes Jun 26, 2025

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nhutnguyenkc added 6 commits June 30, 2025 09:29

soc: renesas: Add support for Renesas RZ/A3M

899eb7d

Add support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

dts: arm: renesas: Add support for Renesas RZ/A3M

e3834f0

Add devicetree to support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

boards: renesas: Add minimal support for board RZ/A3M-EK

f9f70a1

This adds minimal support for board RZ/A3M-EK Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

driver: pinctrl: Add support for Renesas RZ/A3M

3f737f5

Add pinctrl support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

drivers: gpio: Add support for RZ/A3M

7cca64e

Add GPIO driver support for RZ/A3M Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

tests: arch: arm64: arm64_high_address: Exclude Renesas EK-RZ/A3M

b2cfb69

Exclude EK-RZ/A3M board as the redefined CONFIG_SRAM_BASE_ADDRESS degrades the BUILD_OUTPUT_ADJUST_LMA option that will generate a bin file >10GB Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

nhutnguyenkc dismissed stale reviews from binhnguyen2434 and nordicjm via b2cfb69 June 30, 2025 02:30

nhutnguyenkc force-pushed the rza3m_minimal_support branch from bff6cd0 to b2cfb69 Compare June 30, 2025 02:30

github-actions bot removed manifest manifest-hal_renesas DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Jun 30, 2025

nhutnguyenkc closed this Jun 30, 2025

nhutnguyenkc reopened this Jun 30, 2025

nhutnguyenkc modified the milestones: v4.2.0, v4.3.0 Jun 30, 2025

Add minimal support for Renesas EK-RZ/A3M #91031

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Add minimal support for Renesas EK-RZ/A3M #91031

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