Add minimal support for Renesas EK-RZ/A3M

boards/renesas/rza3m_ek/Kconfig.rza3m_ek

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZA3M_EK
+	select SOC_R9A07G066M04GBG

boards/renesas/rza3m_ek/board.cmake

@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G066M04")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+if(CONFIG_BUILD_WITH_RZA_IPL)
+  set(RZA_PLAT a3m)
+  set(RZA_BOARD a3m_ek_nor)
+endif()

boards/renesas/rza3m_ek/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: rza3m_ek
+  full_name: RZ/A3M Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r9a07g066m04gbg

boards/renesas/rza3m_ek/doc/index.rst

@@ -0,0 +1,162 @@
+.. zephyr:board:: rza3m_ek
+
+Overview
+********
+
+The EK-RZ/A3M evaluation kit enables users to easily evaluate the features of the RZ/A3M MPU.
+This kit includes an EK-RZ/A3M board, 5-inch 720x1280 pixel LCD MIPI graphics expansion board, and
+USB cables, allowing the seamless evaluation of high-definition human machine interface (HMI), camera
+input through USB, and more features. Equipped with an on-board J-Link debugger, users can
+conveniently start debugging without additional debuggers.
+Additionally, it also has several expansion connectors such as SDIO, PMOD,and Arduino to connect
+sensors, Wi-Fi, and Bluetooth® Low Energy (LE), allowing users to add more features without
+expanding the board space.
+
+* Special Feature Access
+
+  * MIPI DSI 4 lanes & parallel graphics expansion ports
+  * 5-inch MIPI LCD panel (720x1280 pixels)
+  * USB High-Speed Host & Device
+  * 32MB External QSPI NOR Flash
+  * 128MB External QSPI NAND Flash
+  * External sound codec
+  * External RTC
+
+* MPU Native Pin Access
+
+  * R9A07G066M04GBG MPU
+  * 1GHz, Arm Cortex®-A55 core w/NEON extension
+  * Built-in 128MB DDR3L DRAM
+  * 128KB SRAM w/ECC
+  * 244 pins, BGA package
+  * Native pin access
+  * MPU & USB current measurement
+
+* Ecosystem & System Control Access
+
+  * USB High-Speed Host & Device
+  * 5V input through USB (Debug, HS, USB-PD) or external power supply
+  * Debug on-board (Segger J-Link®)
+  * Debug external (SWD & JTAG)
+  * SCIF download (SWD)
+  * 3 user LEDs & 2 user buttons
+  * 2 SeeedGrove® system (I2C & analog)
+  * 2 Digilent Pmod™ (I2C, SPI or UART selectable)
+  * Arduino™ (Uno R3)
+  * MikroElektronika™ mikroBUS
+  * SparkFun® Qwiic® (I2C)
+  * MPU boot configuration switch
+  * Audio In/Out 4-pole
+  * MicroSD card slot
+
+* Kit Contents
+
+  * EK-RZ/A3M board
+  * MIPI graphics expansion board
+  * USB cable (USB C to USB C)
+  * USB cable (USB A female to USB C)
+  * USB cable (USB A male to USB C)
+  * Screw and spacer for fixing the sub board
+
+Hardware
+********
+The Renesas RZ/A3M MPU documentation can be found at `RZ/A3M Group Website`_
+
+.. figure:: rza3m_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/A3M group feature
+
+	RZ/A3M block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `EK-RZ/A3M Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+EK-RZ/A3M uses Initial Program Loader (IPL) to perform initial settings and copy the Zephyr image from flash to DDR SRAM for execution.
+It only needs to be written to flash at lease once before running Zephyr.
+
+1. For the board setup and connections, follow "3.2 Board Setup" of `Getting Started with RZ/A Flexible Software Package`_.
+
+2. Enable the IPL build with ``-DCONFIG_BUILD_WITH_RZA_IPL=y``.
+   The IPL image ``rza3m_ek_nor_ipl.bin`` is generated under zephyrproject/zephyr/build/rza_ipl/a3m/release
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza3m_ek
+   :goals: build
+   :gen-args: -DCONFIG_BUILD_WITH_RZA_IPL=y
+
+.. note::
+   Currently, the IPL source code can built on Linux environment only.
+   For Windows, please follow `Initial Program Loader Application Note`_
+
+3. Flash it onto the board at address 0x20000000 by Jlink command `Segger JLink Renesas R9A07G066`_
+
+.. code-block:: console
+
+   $ JLinkExe
+   J-Link> connect
+   Device> R9A07G066M04
+   TIF> s
+   Speed> [Enter]
+   J-Link> h
+   J-Link> loadfile <ipl_bin_path> 0x20000000
+
+Where ``<ipl_bin_path>`` is the path to the ``rza3m_ek_nor_ipl.bin`` in the output directory.
+
+Applications for the ``rza3m_ek`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+Console
+=======
+The UART port is accessed by USB Debug connector (J10).
+
+Debugging
+=========
+
+It is possible to load and execute a Zephyr application binary on this board on the Cortex-A55 System Core
+from the DDR SDRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza3m_ek
+   :goals: build debug
+
+Flashing
+========
+
+Zephyr application can be flashed to Quad-SPI storage and then loaded by Initial Program Loader.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza3m_ek
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/A3M Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3m-powerful-1ghz-mpus-built-ddr3l-sdram-high-definition-hmi
+
+.. _EK-RZ/A3M Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/ek-rza3m-evaluation-kit-rza3m-mpu
+
+.. _Initial Program Loader Application Note:
+   https://github.com/renesas/rza-initial-program-loader/tree/main/application_note
+
+.. _Getting Started with RZ/A Flexible Software Package:
+   https://www.renesas.com/en/document/apn/rza-getting-started-flexible-software-package
+
+.. _Segger JLink Renesas R9A07G066:
+   https://kb.segger.com/Renesas_R9A07G066

boards/renesas/rza3m_ek/rza3m_ek-pinctrl.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza3m.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif0_pins: scif0 {
+		scif0-pinmux {
+			pinmux = <RZA_PINMUX(PORT_06, 0, 2)>, /* RXD */
+				 <RZA_PINMUX(PORT_06, 1, 2)>; /* TXD */
+			drive-strength = <1>;
+			slew-rate = "fast";
+		};
+	};
+};

boards/renesas/rza3m_ek/rza3m_ek.dts

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
+#include <freq.h>
+#include <arm64/renesas/rz/rza/r9a07g066.dtsi>
+#include "rza3m_ek-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZ/A3M EK";
+	compatible = "renesas,rza3m-ek";
+
+	chosen {
+		zephyr,sram = &ddr;
+		zephyr,flash = &spi_flash;
+		zephyr,console = &scif0;
+		zephyr,shell-uart = &scif0;
+		zephyr,code-partition= &slot0_partition;
+	};
+
+	ddr: memory@40200000 {
+		compatible ="zephyr,memory-region", "mmio-sram";
+		reg = <0x40200000 (DT_SIZE_M(128) - 0x200000)>;
+		zephyr,memory-region = "DDR";
+	};
+
+	sram: memory@1e000 {
+		compatible ="zephyr,memory-region", "mmio-sram";
+		reg = <0x1e000 DT_SIZE_K(72)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	spi_flash: memory@20020000 {
+		compatible = "mmio-sram";
+		reg = <0x20020000 (DT_SIZE_M(16) - 0x20000)>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			header: partition@0 {
+				label = "header";
+				reg = <0x00000000 0x200>;
+				read-only;
+			};
+
+			slot0_partition: partition@200 {
+				label = "image-0";
+				reg = <0x00000200 (DT_SIZE_M(16) - 0x20200)>;
+				read-only;
+			};
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		sw0 = &sw1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&gpio10 1 GPIO_ACTIVE_HIGH>;
+			label = "led1";
+		};
+
+		led2: led2 {
+			gpios = <&gpio20 3 GPIO_ACTIVE_HIGH>;
+			label = "led2";
+		};
+
+		led3: led3 {
+			gpios = <&gpio20 4 GPIO_ACTIVE_HIGH>;
+			label = "led3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		sw1: sw1 {
+			label = "sw1";
+			gpios = <&gpio10 3 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		sw2: sw2 {
+			label = "sw2";
+			gpios = <&gpio11 1 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&scif0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio10 {
+	status = "okay";
+};
+
+&gpio11 {
+	status = "okay";
+};
+
+&gpio20 {
+	status = "okay";
+};

boards/renesas/rza3m_ek/rza3m_ek.yaml

@@ -0,0 +1,13 @@
+identifier: rza3m_ek
+name: Renesas RZ/A3M Evaluation Kit
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+supported:
+  - uart
+  - gpio
+testing:
+  ignore_tags:
+    - bluetooth

boards/renesas/rza3m_ek/rza3m_ek_defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# MMU Options
+CONFIG_MAX_XLAT_TABLES=24
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

drivers/gpio/gpio_renesas_rz.h

@@ -15,7 +15,7 @@
 #if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) ||                       \
 	defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) ||                    \
 	defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) ||                   \
-	defined(CONFIG_SOC_SERIES_RZV2N)
+	defined(CONFIG_SOC_SERIES_RZV2N) || defined(CONFIG_SOC_SERIES_RZA3M)
 #include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
 
 #if defined(CONFIG_SOC_SERIES_RZG3S)
@@ -40,6 +40,18 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0,  4,  9,  13, 17, 23
 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0,  4,  9,  13, 17, 23, 28, 33, 38, 43,
 							  47, 52, 56, 58, 63, 66, 70, 72, 76};
 
+#elif defined(CONFIG_SOC_SERIES_RZA3M)
+#define GPIO_RZ_P_REG_BASE_GET                  (&R_GPIO->P01)
+#define GPIO_RZ_PM_REG_BASE_GET                 (&R_GPIO->PM01)
+#define GPIO_RZ_PFC_REG_BASE_GET                (&R_GPIO->PFC01)
+#define GPIO_RZ_MAX_PORT_NUM                    24
+#define GPIO_RZ_TINT_IRQ_OFFSET                 476
+#define R_INTC                                  R_INTC_IA55
+#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IA55->TSCR &= ~BIT(tint_num))
+static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0,  4,  9,  13, 17, 23, 28, 33, 38, 42,
+							  47, 52, 56, 0,  0,  0,  0,  0,  0,  0,
+							  58, 64, 67, 72};
+
 #elif defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZV2N)
 #define GPIO_RZ_P_REG_BASE_GET      (&R_GPIO->P20)
 #define GPIO_RZ_PM_REG_BASE_GET     (&R_GPIO->PM20)