drivers: spi: add cadence spi driver #85973
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XenuIsWatching
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uhh.... but you requested changes? |
This provides a driver for the cadence spi. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
As there is no currently known board that has the cadence spi, add a test to just build it under the qemu cortex m3. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Humpf... Ticked the wrong box. |
| uint8_t fifo_width; | ||
| uint16_t rx_fifo_depth; | ||
| uint16_t tx_fifo_depth; |
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I find some bug in the spi_cdns.c as I see you are using above variables from spi_cdns_cfg structure for decision making but nowhere assigned.
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I have used your repo and tried initialized these variables like below
.fifo_width = DT_INST_PROP(n, fifo_width), \
.tx_fifo_depth = DT_INST_PROP(n, tx_fifo_depth), \
.rx_fifo_depth = DT_INST_PROP(n, rx_fifo_depth),with dt node
&spi1 {
status = "okay";
clock-frequency = <200000000>;
fifo-width = <8>;
rx-fifo-depth = <128>;
tx-fifo-depth = <128>;
flash@2 {
compatible = "jedec,spi-nor";
reg = <2>;
spi-max-frequency = <8000000>;
jedec-id = [ c2 25 36 ]; /* mx25u3235f */
size = <0x2000000>; /* 32Mb */
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <35000>;
};
};
and tested on AMD hardware with spi-nor ztest , I see testes are failled
Running TESTSUITE flash_driver
START - test_flash_copy
Test will run on device flash@2
Assertion failed at WEST_TOPDIR/zephyr/tests/drivers/flash/common/src/main.c:65: flash_driver_before: device_is_ready(flash_dev) is false
FAIL - test_flash_copy in 0.016 seconds
seems like transfer is not happening properly.
Command used for build:
west build -p always -b versal_net_rpu tests/drivers/flash/common/ --force
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hmm... that's embarrassing... those where there in my local repo, but it appears those lines disappeared when coping over to my forked repo 🤦
Those lines you added appear correct, I'll get a PR up to add those one (as well as that missing spi rtio fallback). if i had to guess, I'd assume it's probably still related to the fifo calcuations as to why it's failing. Are you able to look into why that is failing?
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@XenuIsWatching What hardware/IP core version was this driver tested against? The AMD/Xilinx MPSoC apparently has r109 and it seems like this driver references some control register bits that are not defined on that version.
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This is against r112
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Yes, I have hardware, but I can't say anything about it...
If you're using r109 (as this was tested against r112) which I see that's what it has for you're hardware here https://docs.amd.com/r/en-US/am011-versal-acap-trm/SPI-Controller-Implementation, then you can make the minor modifications to code and to make it compile between the two and submit a PR once you've got that.
There is a follow-up fix PR as well for this #88777
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Hi @XenuIsWatching
I am also using the same version(r112) , I tried the with #88777 , could able build without any change, but I see issue in the runtime that driver is failing with time out error during initializing the flash_node attached as child under SPI.
like as below:
E: Timeout waiting for transfer complete
E: Failed to exit DPD (-116)
I tested my hardware setup with #87382 all tests are working fine.
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Are you able to just debug it? I'm on PTO this week..
What SoC are you using?
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There may be an issue with the spi clock divisor calculation as that was ported from originally working with #89124
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I found there is an issue, I'll try to get a fix soon for the spi clk divisor, it'll just be an additional commit on top of that existing PR fix
This provides a driver for the cadence spi