dts: xilinx: add cadence spi controllers to zynqmp.dtsi

[singular0770]

Adds spi controller nodes for Cadence SPI controllers in zynqmp.dtsi. A driver for the Cadence SPI peripheral on AMD devices was recently merged into Zephyr, this PR adds support for those peripherals on ZynqMP devices. The driver was confirmed to be functional on a ZUBoard 1CG (XCZU1CG) with the fix in PR 88777.

[henrikbrixandersen]

Shouldn't this wait until #88777 was merged, then?

[singular0770]

Shouldn't this wait until #88777 was merged, then?

The driver in its initial state has already been merged. Yes, software making use of this driver won't be functional until #88777 gets merged, but seeing as the driver is already available to the build system I don't particularly see why we this change needs to wait in the meantime.

[henrikbrixandersen]

Shouldn't this wait until #88777 was merged, then?

The driver in its initial state has already been merged. Yes, software making use of this driver won't be functional until #88777 gets merged, but seeing as the driver is already available to the build system I don't particularly see why we this change needs to wait in the meantime.

Merging the changes in this PR without the fix in #88777 will let users enable the SPI hardware in their board DTS, but it will not be functional - correct? If so, we need to merge them in the right order.

[singular0770]

Shouldn't this wait until #88777 was merged, then?

The driver in its initial state has already been merged. Yes, software making use of this driver won't be functional until #88777 gets merged, but seeing as the driver is already available to the build system I don't particularly see why we this change needs to wait in the meantime.

Merging the changes in this PR without the fix in #88777 will let users enable the SPI hardware in their board DTS, but it will not be functional - correct? If so, we need to merge them in the right order.

It will build but not run correctly. Putting this PR in draft state as I don't see a way to add dependencies on other PRs. Will take out of draft when #88777 gets merged.

[robhancocksed]

LGTM, we are using essentially the same definitions without issues.

[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

[henrikbrixandersen]

Are there no board, where SPI should now be enabled?

[michalsimek]

Are there no board, where SPI should now be enabled?

We have this driver on our list to test. And we will do wiring in all of our hard SOCs in QEMU.

[singular0770]

Are there no board, where SPI should now be enabled?

Right now there are only three boards upstream (1 QEMU) that use the ZynqMP RPU. As far as I can tell none have a great use case for this. I have a separate PR open to add support for the Avnet ZUBoard 1CG which does have a SPI pressure sensor, so once this gets merged I can definitely update that PR to enable the SPI bus.