Add support for cadence SPI #87382
Add support for cadence SPI #87382
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Hello @SrikanthGoud123, and thank you very much for your first pull request to the Zephyr project! |
Add devicetree binding for the Cadence SPI IP. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Message-ID: <20250319100832.3986031-2-srikanth.boyapally@amd.com> State: pending
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drivers/spi/spi_cdns.c
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| mm_reg_t base; | ||
| void (*irq_config_func)(const struct device *dev); | ||
| uint8_t num_ss_bits; | ||
| uint32_t is_decoded_cs; |
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Change this 2 attributes to uint6_t, for better alignment.
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made changes as per you suggested
drivers/spi/spi_cdns.c
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| }; | ||
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| struct cdns_spi_data { | ||
| uint16_t slave; |
drivers/spi/spi_cdns.c
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| cdns_spi_cs_cntrl(dev, true); | ||
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| #ifdef CONFIG_CDNS_SPI_INTR | ||
| do { |
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in this case, fifo r/w should happen in the isr. Or else, here it's going to do a back & forth between isr/user thread etc etc... thus more overhead.
It should just enable the interrupt, and wait for completion.
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Hi @tbursztyka
Thanks for the review.
changed the logic as per your suggestion.
Introduces the Cadence SPI IP driver. By adding support for master mode, the SPI controller enables the communications with variety of peripherals such as SPI-NOR flash memories, eeprom and Trusted Platform Module(TPM) devices and other peripherals. Additionally, the controller can operate in an external loopback test mode. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Message-ID: <20250319100832.3986031-3-srikanth.boyapally@amd.com> State: pending
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Just realized @XenuIsWatching has made a previous PR about the same hw, in #85973 You'll need to sync. My position would be : first come first served. |
Add devicetree binding for the Cadence SPI IP. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Message-ID: <20250319100832.3986031-2-srikanth.boyapally@amd.com> Link: zephyrproject-rtos/zephyr#87382 State: waiting
Introduces the Cadence SPI IP driver. By adding support for master mode, the SPI controller enables the communications with variety of peripherals such as SPI-NOR flash memories, eeprom and Trusted Platform Module(TPM) devices and other peripherals. Additionally, the controller can operate in an external loopback test mode. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Message-ID: <20250319100832.3986031-3-srikanth.boyapally@amd.com> Link: zephyrproject-rtos/zephyr#87382 State: waiting
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This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time. |
Introduces the Cadence SPI IP driver and dt bindings. By adding support for master mode, the SPI controller enables the communications with variety of peripherals such as SPI-NOR flash memories, eeprom and Trusted Platform Module(TPM) devices and other peripherals. Additionally, the controller can operate in an external loopback test mode