CircuitVerse Primary Code Base

A free, open source, online digital circuit/logic designer.

复旦大学 数字逻辑与部件设计实验 2020秋

交通大學iclab 2023 fall

Designing of digital circuits based on problems in digital electronics, implemented in logic.ly simulator

Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.

This project showcases the design of a single cycle central processing unit which was built using the logisim.

Repository for open-source tools to VLSI design

A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.

RV32I 5-Stage Pipelined CPU

Verilog codes developed as a part of COA lab course

Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method

Digital circuit for Tetris game without microcontrollers.

Verilog HDL implementation and verification of a controller unit of washing machine.

This repository contains the projects which I created using Verilog

custom clock made in logisim

Processor Design of RV32I Single Cycle CPU

Freshman course DCD in NYCU; 2022

Este repositorio es la exploración de la electrónica digital en sistemas informáticos: bits, Álgebra Booleana y biestables. Recursos y ejemplos para el diseño de circuitos y componentes clave como memorias y contadores.