[RISCV] Add UnsupportedSchedXXX for vendor extensions package

[wangpc-pp]

There will be more schedule definitions for vendor extentions and
we need add these UnsupportedSchedXXX to exsiting models every
we add new schedule definitions.

The fact is that each vendor will barely implement other vendors'
extensions, so we can package these definitions into one.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

Changes

There will be more schedule definitions for vendor extentions and
we need add these UnsupportedSchedXXX to exsiting models every
we add new schedule definitions.

The fact is that each vendor will barely implement other vendors'
extensions, so we can package these definitions into one.

---

Full diff: https://github.com/llvm/llvm-project/pull/147666.diff

15 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVSchedAndes45.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td (+2-3)
• (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td (+1-2)
• (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+6)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index f42b48a1d8b83..8489801fbb60a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -328,12 +328,11 @@ def : ReadAdvance<ReadCSR, 0>;
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedQ;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
index 6dd973bc1e83f..52cbcad7f758f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
@@ -496,6 +496,5 @@ defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedZvk;
-defm : UnsupportedSchedSFB;
-defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index 8ba4cd0acdd6c..4ba878046d6a2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -271,8 +271,7 @@ defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfhmin;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZabha;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 4c4654ba2fc0f..3273abf4deceb 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -261,7 +261,6 @@ defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfhmin;
-defm : UnsupportedSchedSFB;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 370ea64699383..32b547872a1cd 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -1236,7 +1236,6 @@ defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
index 5933d73174f79..ff6527c895ed8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
@@ -355,8 +355,7 @@ defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
-defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 7c04d1c54473d..6e58def194798 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -1492,7 +1492,6 @@ defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index f2b660583f27f..b8d8d716a23db 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -1181,7 +1181,6 @@ defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfaWithQ;
-defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 9059d5a4e497b..94382af18875a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -345,11 +345,10 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 // Unsupported extensions
 defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
-defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
index 4aa74b020825c..2a08e4a47b104 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -106,7 +106,6 @@ def : ReadAdvance<ReadIMul32, 0>;
 // Unsupported extensions
 defm : UnsupportedSchedA;
 defm : UnsupportedSchedF;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZba;
@@ -116,6 +115,6 @@ defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
index 815c2da992a11..954ef164da314 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
@@ -180,9 +180,7 @@ multiclass SCR_Other {
 
 // Unsupported scheduling classes for SCR3-5.
 multiclass SCR_Unsupported :
-  UnsupportedSchedSFB,
   UnsupportedSchedV,
-  UnsupportedSchedXsfvcp,
   UnsupportedSchedZabha,
   UnsupportedSchedZba,
   UnsupportedSchedZbb,
@@ -191,7 +189,8 @@ multiclass SCR_Unsupported :
   UnsupportedSchedZbkb,
   UnsupportedSchedZbkx,
   UnsupportedSchedZfa,
-  UnsupportedSchedZvk;
+  UnsupportedSchedZvk,
+  UnsupportedSchedXsf;
 
 multiclass SCR3_Unsupported :
   SCR_Unsupported,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
index decd578360753..b9c8e61785c97 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
@@ -242,13 +242,12 @@ multiclass SCR7_Other {
 // Unsupported scheduling classes for SCR7.
 multiclass SCR7_Unsupported {
   defm : UnsupportedSchedQ;
-  defm : UnsupportedSchedSFB;
   defm : UnsupportedSchedV;
-  defm : UnsupportedSchedXsfvcp;
   defm : UnsupportedSchedZabha;
   defm : UnsupportedSchedZfa;
   defm : UnsupportedSchedZfhmin;
   defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
 }
 
 
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 5322de100d0ad..d1ab4bb0bb4d5 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -320,12 +320,11 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 // Unsupported extensions
 defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
-defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
index 3076a2ebb813d..6ca896e89afe8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
@@ -310,8 +310,7 @@ defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfhmin;
-defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZabha;
-defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 4d49ad4d6b317..061abc54003cb 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -519,3 +519,9 @@ include "RISCVScheduleZb.td"
 include "RISCVScheduleV.td"
 include "RISCVScheduleXSf.td"
 include "RISCVScheduleZvk.td"
+
+// Vendor Extensions
+multiclass UnsupportedSchedXsf {
+  defm : UnsupportedSchedSFB;
+  defm : UnsupportedSchedXsfvcp;
+}