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[LV] Remove common extends and selects in CSE

backend:PowerPC

backend:RISC-V

llvm:ir

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 147731

#147731 In llvm/llvm-project;

· SamTebbs33 opened on Jul 9, 2025

[RISCV][RFC] Add additional opcodes to RISCVDAGToDAGISel::hasAllNBitUsers

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147728

#147728 In llvm/llvm-project;

· asb opened on Jul 9, 2025

[ISel/RISCV] Custom-lower vector [l]lround

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147713

#147713 In llvm/llvm-project;

· artagnon opened on Jul 9, 2025

[RISCV] Add UnsupportedSchedXXX for vendor extensions package

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147666

#147666 In llvm/llvm-project;

· wangpc-pp opened on Jul 9, 2025

[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:SystemZ

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147664

#147664 In llvm/llvm-project;

· BoyaoWang430 opened on Jul 9, 2025

[RISCV] Add ISel patterns for Xqciac QC.MULIADD instruction

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147661

#147661 In llvm/llvm-project;

· svs-quic opened on Jul 9, 2025

[RISCV] Add Commutable flag to XNOR.

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147654

#147654 In llvm/llvm-project;

· topperc opened on Jul 9, 2025

Add support for remaining pseudos in RISCVVLOptimizer

backend:RISC-V

Status: Open.

#147647 In llvm/llvm-project;

· lukel97 opened on Jul 9, 2025

[LegalizeTypes] Preserve disjoint flag when expanding OR.

backend:RISC-V

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147640

#147640 In llvm/llvm-project;

· topperc opened on Jul 9, 2025

[RISCV] Optimize (and (icmp x, 0, eq), (icmp y, 0, eq)) utilizing zicond extension

backend:AArch64

backend:RISC-V

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 147627

#147627 In llvm/llvm-project;

· bababuck opened on Jul 9, 2025

[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 147626

#147626 In llvm/llvm-project;

· mshockwave opened on Jul 9, 2025

MachineLICM: Merge logic for implicit and explicit definitions.

backend:AArch64

backend:AMDGPU

backend:RISC-V

backend:X86

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 147624

#147624 In llvm/llvm-project;

· pcc opened on Jul 9, 2025