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[RISCV] Add UnsupportedSchedXXX for vendor extensions package #147666

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[RISCV] Add UnsupportedSchedXXX for vendor extensions package #147666

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3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedAndes45.td
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Expand Up @@ -328,12 +328,11 @@ def : ReadAdvance<ReadCSR, 0>;
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
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Expand Up @@ -496,6 +496,5 @@ defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedZfaWithQ;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
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Expand Up @@ -271,8 +271,7 @@ defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedRocket.td
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Expand Up @@ -261,7 +261,6 @@ defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
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Expand Up @@ -1236,7 +1236,6 @@ defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
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Expand Up @@ -355,8 +355,7 @@ defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbs;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
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Expand Up @@ -1492,7 +1492,6 @@ defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
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Expand Up @@ -1181,7 +1181,6 @@ defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfaWithQ;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
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Expand Up @@ -345,11 +345,10 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
// Unsupported extensions
defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
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Expand Up @@ -106,7 +106,6 @@ def : ReadAdvance<ReadIMul32, 0>;
// Unsupported extensions
defm : UnsupportedSchedA;
defm : UnsupportedSchedF;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedV;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZba;
Expand All @@ -116,6 +115,6 @@ defm : UnsupportedSchedZbs;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsf;
}
5 changes: 2 additions & 3 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
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Expand Up @@ -180,9 +180,7 @@ multiclass SCR_Other {

// Unsupported scheduling classes for SCR3-5.
multiclass SCR_Unsupported :
UnsupportedSchedSFB,
UnsupportedSchedV,
UnsupportedSchedXsfvcp,
UnsupportedSchedZabha,
UnsupportedSchedZba,
UnsupportedSchedZbb,
Expand All @@ -191,7 +189,8 @@ multiclass SCR_Unsupported :
UnsupportedSchedZbkb,
UnsupportedSchedZbkx,
UnsupportedSchedZfa,
UnsupportedSchedZvk;
UnsupportedSchedZvk,
UnsupportedSchedXsf;

multiclass SCR3_Unsupported :
SCR_Unsupported,
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3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
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Expand Up @@ -242,13 +242,12 @@ multiclass SCR7_Other {
// Unsupported scheduling classes for SCR7.
multiclass SCR7_Unsupported {
defm : UnsupportedSchedQ;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsf;
}


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3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
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Expand Up @@ -320,12 +320,11 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
// Unsupported extensions
defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsf;
}
3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
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Expand Up @@ -310,8 +310,7 @@ defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedXsfvcp;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedXsf;
}
6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedule.td
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Expand Up @@ -519,3 +519,9 @@ include "RISCVScheduleZb.td"
include "RISCVScheduleV.td"
include "RISCVScheduleXSf.td"
include "RISCVScheduleZvk.td"

// Vendor Extensions
multiclass UnsupportedSchedXsf {
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsfvcp;
}