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Merge upstream/v1.1.1 into VHDL port #43

Merge upstream/v1.1.1 into VHDL port

Merge upstream/v1.1.1 into VHDL port #43

Triggered via push September 18, 2025 14:26
Status Success
Total duration 1m 27s
Artifacts 1

build.yml

on: push
Matrix: test
finish_coveralls
12s
finish_coveralls
Build distributions
18s
Build distributions
deploy
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dist
665 KB
sha256:456751cccbbadec6c52bf4b92b22545200c60b0a357953f46b5dea811d0d8cfd