Merge upstream/v1.1.1 into VHDL port

Author: darsor

docs/conf.py

@@ -49,7 +49,17 @@
 # The theme to use for HTML and HTML Help pages.  See the documentation for
 # a list of builtin themes.
 #
-html_theme = "sphinx_rtd_theme"
+html_theme = "sphinx_book_theme"
+
+html_theme_options = {
+    "repository_url": "https://github.com/SystemRDL/PeakRDL-regblock-vhdl",
+    "path_to_docs": "docs",
+    "use_download_button": False,
+    "use_source_button": True,
+    "use_repository_button": True,
+    "use_issues_button": True,
+}
+
 
 # Add any paths that contain custom static files (such as style sheets) here,
 # relative to this directory. They are copied after the builtin static files,

docs/cpuif/internal_protocol.rst

@@ -44,7 +44,7 @@ cpuif_req_stall_rd
     transfer will not be accepted until this signal is deasserted.
 
 cpuif_req_stall_wr
-    If asserted, and the next pending request is a read operation, then the
+    If asserted, and the next pending request is a write operation, then the
     transfer will not be accepted until this signal is deasserted.
 
 

docs/requirements.txt

@@ -1,3 +1,3 @@
 pygments-systemrdl
 sphinxcontrib-wavedrom
-sphinx-rtd-theme
+sphinx-book-theme

src/peakrdl_regblock_vhdl/__about__.py

@@ -1,2 +1,2 @@
-version_info = (1, 1, 0, 0)
+version_info = (1, 1, 1, 0)
 __version__ = ".".join([str(n) for n in version_info])

src/peakrdl_regblock_vhdl/cpuif/apb3/apb3_tmpl.vhd

@@ -1,10 +1,10 @@
 {%- if cpuif.is_interface -%}
 -- pragma translate_off
 cpuif_generics: process begin
-    assert {{cpuif.signal("paddr")}}'length >= {{ds.module_name.upper()}}_MIN_ADDR_WIDTH
+    assert_bad_addr_width: assert {{cpuif.signal("paddr")}}'length >= {{ds.module_name.upper()}}_MIN_ADDR_WIDTH
         report "Interface address width of " & integer'image({{cpuif.signal("paddr")}}'length) & " is too small. Shall be at least " & integer'image({{ds.module_name.upper()}}_MIN_ADDR_WIDTH) & " bits"
         severity failure;
-    assert {{cpuif.signal("pwdata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
+    assert_bad_data_width: assert {{cpuif.signal("pwdata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
         report "Interface data width of " & integer'image({{cpuif.signal("pwdata")}}'length) & " is incorrect. Shall be " & integer'image({{ds.module_name.upper()}}_DATA_WIDTH) & " bits"
         severity failure;
     wait;

src/peakrdl_regblock_vhdl/cpuif/apb4/apb4_tmpl.vhd

@@ -1,10 +1,10 @@
 {%- if cpuif.is_interface -%}
 -- pragma translate_off
 cpuif_generics: process begin
-    assert {{cpuif.signal("paddr")}}'length >= {{ds.module_name.upper()}}_MIN_ADDR_WIDTH
+    assert_bad_addr_width: assert {{cpuif.signal("paddr")}}'length >= {{ds.module_name.upper()}}_MIN_ADDR_WIDTH
         report "Interface address width of " & integer'image({{cpuif.signal("paddr")}}'length) & " is too small. Shall be at least " & integer'image({{ds.module_name.upper()}}_MIN_ADDR_WIDTH) & " bits"
         severity failure;
-    assert {{cpuif.signal("pwdata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
+    assert_bad_data_width: assert {{cpuif.signal("pwdata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
         report "Interface data width of " & integer'image({{cpuif.signal("pwdata")}}'length) & " is incorrect. Shall be " & integer'image({{ds.module_name.upper()}}_DATA_WIDTH) & " bits"
         severity failure;
     wait;

src/peakrdl_regblock_vhdl/cpuif/avalon/avalon_tmpl.vhd

@@ -1,10 +1,10 @@
 {%- if cpuif.is_interface -%}
 -- pragma translate_off
 cpuif_generics: process begin
-    assert {{cpuif.signal("address")}}'length >= {{cpuif.word_addr_width}}
+    assert_bad_addr_width: assert {{cpuif.signal("address")}}'length >= {{cpuif.word_addr_width}}
         report "Interface address width of " & integer'image({{cpuif.signal("address")}}'length) & " is too small. Shall be at least " & integer'image({{cpuif.word_addr_width}}) & " bits"
         severity failure;
-    assert {{cpuif.signal("writedata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
+    assert_bad_data_width: assert {{cpuif.signal("writedata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
         report "Interface data width of " & integer'image({{cpuif.signal("writedata")}}'length) & " is incorrect. Shall be " & integer'image({{ds.module_name.upper()}}_DATA_WIDTH) & " bits"
         severity failure;
     wait;

src/peakrdl_regblock_vhdl/cpuif/axi4lite/axi4lite_tmpl.vhd

@@ -1,10 +1,10 @@
 {%- if cpuif.is_interface -%}
 -- pragma translate_off
 cpuif_generics: process begin
-    assert {{cpuif.signal("araddr")}}'length >= {{ds.module_name.upper()}}_MIN_ADDR_WIDTH
+    assert_bad_addr_width: assert {{cpuif.signal("araddr")}}'length >= {{ds.module_name.upper()}}_MIN_ADDR_WIDTH
         report "Interface address width of " & integer'image({{cpuif.signal("araddr")}}'length) & " is too small. Shall be at least " & integer'image({{ds.module_name.upper()}}_MIN_ADDR_WIDTH) & " bits"
         severity failure;
-    assert {{cpuif.signal("wdata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
+    assert_bad_data_width: assert {{cpuif.signal("wdata")}}'length = {{ds.module_name.upper()}}_DATA_WIDTH
         report "Interface data width of " & integer'image({{cpuif.signal("wdata")}}'length) & " is incorrect. Shall be " & integer'image({{ds.module_name.upper()}}_DATA_WIDTH) & " bits"
         severity failure;
     wait;

src/peakrdl_regblock_vhdl/hwif/__init__.py

@@ -50,7 +50,7 @@ def top_node(self) -> AddrmapNode:
 
 
     def get_extra_package_params(self) -> str:
-        lines = []
+        lines = [""]
 
         for param in self.top_node.inst.parameters:
             value = param.get_value()
@@ -70,7 +70,7 @@ def get_package_contents(self) -> str:
         """
         If this hwif requires a package, generate the string
         """
-        lines = []
+        lines = [""]
 
         gen_in = self._gen_in_cls(self)
         structs_in = gen_in.get_struct(

src/peakrdl_regblock_vhdl/module_tmpl.vhd

@@ -153,9 +153,9 @@ begin
                     external_pending <= '0';
                 end if;
                 --pragma translate_off
-                assert not external_wr_ack or (external_pending or external_req)
+                assert_bad_ext_wr_ack: assert not external_wr_ack or (external_pending or external_req)
                     report "An external wr_ack strobe was asserted when no external request was active";
-                assert not external_rd_ack or (external_pending or external_req)
+                assert_bad_ext_rd_ack: assert not external_rd_ack or (external_pending or external_req)
                     report "An external rd_ack strobe was asserted when no external request was active";
                 --pragma translate_on
             end if;