I’m B M Madhumitha, a driven VLSI enthusiast with a B.Tech in Electronics and Communication Engineering (VLSI specialization) and a Minor in Computer Science from PES University, Bengaluru. My work and research focus on pushing the boundaries of digital design, hardware acceleration, and semiconductor verification.
- Research Intern at SINESys Lab, Indian Institute of Science (IISc), low-power hardware accelerators for solving PDEs leveraging Sky130A, OpenLane, and Accelergy.
- Hands-on expertise in full RTL-to-GDSII flow (Yosys, Openlane, Icarus Verilog, OpenRoad), UVM-based functional and formal verification, RTL Simulation, and FPGA prototyping.
- Selected as part of the prestigious NXP Women in Tech program (Top 50 nationwide), trained in advanced semiconductor design methodologies.
- ASIC & SoC Design: RTL coding, timing optimization, layout-aware design.
- Functional Verification: Developing reusable UVM testbenches, DFT, and robust validation techniques.
- Computer Architecture: Modeling and simulation of RISC-V and x86 pipelines.
- Analog & Mixed Signal Design: Designing SAR ADCs, PRBS Generators, and dynamic analog circuits in Cadence Virtuoso.
- Open Source EDA Tools: Skilled with OpenLane, Yosys, KLayout, Magic, and others for physical design automation.
Innovating memory and computation architectures for efficient, resource-optimized integration. Advancing secure, real-time systems to enable reliable hardware solutions in dynamic environments.
| Repository Name | Description | Tools |
|---|---|---|
| 3_bit_SAR_ADC | Design and simulation of a 3-bit Successive Approximation Register ADC. | Cadence Virtuoso |
| PRBS | Pseudo-Random Bit Sequence generator, used in BIST and data integrity checks. | LTSpice, Verilog Simulation |
| Cordic | Hardware implementation of the CORDIC algorithm for trigonometric computations. | Cadence Xcelium, ncverilog, Stratus |
| control_system | Explores the design of an automated steering controller aimed at improving vehicle safety and reducing driver workload. The project is divided into three phases: a simplified initial control model, integration of feedback mechanisms with accelerometer data to analyze stability and performance, and final consideration of wind gust disturbances alongside accelerometer feedback to enhance system robustness. | MATLAB |
| DFT_for_Asynchronous_FIFO | Scan insertion and DFT techniques applied to asynchronous FIFO designs. | Cadence Genus, Modus |
| weighted_rr | Weighted Round-Robin Arbiter implementation for bus access management. | Cadence Xcelium, ncverilog, Genus |
| fibonacci | Hardware-efficient Fibonacci number generator using SystemVerilog. | UVM, Cadence IMC |
| RISC_V_Single_cycle_processor | RTL design of a single-cycle RISC-V processor core. | Cadence Genus, Jaspergold, Conformal Equivalence Checker |
Contact Me:
- Email: madhumithabm2003@gmail.com
- GitHub: B M Madhumitha
- LinkedIn: B M Madhumitha