3_bit_SAR_ADC

The successive approximation converter performs basically a binary search through all possible quantization levels before converging on the final digital answer. An N-bit register controls the timing of the conversion where N is the resolution of the ADC. VIN is sampled and compared to the output of the DAC. The comparator output controls the direction of the binary search, and the output of the successive approximation register (SAR) is the actual digital conversion.

Successive Approximation Algorithm:

Circuits to build 3 bit SAR ADC

comparator

shift register

D flip flop

JK flip flop

Sample and Hold

DAC (Digital to Analog Converter)

SAR logic when Din= 111

SAR logic when Din= 000

3 bit SAR ADC:

Internal clock generator:

Delay cell:

2 input NAND Gate:

3 input NAND Gate:

OR gate:

XOR Gate:

Inverter:

Prepared By:

B M Madhumitha

References:

1. CMOS circuit design, layout and simulation - R Jacob Baker
2. CMOS Analog Integrated circuits Data Converters, Phase locked loops, and their applications – Tertulien Ndjountche