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stm32mp2: add wwdg1 and iwdg4 support #92319

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stm32mp2: add wwdg1 and iwdg4 support #92319

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9f305a1
drivers: wdt_wwdg_stm32: freeze watchdog in debug mode for mp2x SoCs
lucbeaufils Jun 19, 2025
d97c979
dt-bindings: stm32mp2_clock: add wwdg1 clock
lucbeaufils Jun 19, 2025
55ec92c
dts: arm: stm32mp2_m33: add wwdg1 node
lucbeaufils Jun 19, 2025
2c8a31e
clock_control: clock_stm32_ll_mp2: add wwdg1 clock support
lucbeaufils Jun 24, 2025
6d01da7
drivers: wdt_iwdg_stm32.c: freeze watchdog in debug mode for mp2x SoCs
lucbeaufils Jun 19, 2025
beaae5b
dt-bindings: stm32mp2_clock: add iwdg4 clock
lucbeaufils Jun 19, 2025
344a37f
dts: arm: stm32mp2_m33.dtsi: add iwdg4 watchdog node
lucbeaufils Jun 19, 2025
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5 changes: 5 additions & 0 deletions drivers/clock_control/clock_stm32_ll_mp2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,11 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
case STM32_CLOCK_PERIPH_UART9:
*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE);
break;
case STM32_CLOCK_PERIPH_WWDG1:
/* The WWDG1 clock is derived from the APB3 clock */
int wwdg1_clock = 400000000 >> LL_RCC_Get_LSMCUDIVR();
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Here we should be able to retrieve the frequency instead of hardcoding it.
Seems that it is not implemented in LL.

@erwango : any advice to solve this?

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In STM32 MCU ports, this value comes from DT. So you can put in DT, but it should be somehow sync'ed with A4.
Alternatively, you may have HAL functions to query it.

*rate = wwdg1_clock >> LL_RCC_GetAPB3Prescaler();
break;
default:
return -ENOTSUP;
}
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2 changes: 2 additions & 0 deletions drivers/watchdog/wdt_iwdg_stm32.c
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Expand Up @@ -105,6 +105,8 @@ static int iwdg_stm32_setup(const struct device *dev, uint8_t options)
LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG1_STOP);
#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG_STOP);
#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_IWDG4_STOP);
#else
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP);
#endif
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2 changes: 1 addition & 1 deletion drivers/watchdog/wdt_wwdg_stm32.c
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Expand Up @@ -173,7 +173,7 @@ static int wwdg_stm32_setup(const struct device *dev, uint8_t options)
#elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
#endif
#if defined(CONFIG_SOC_SERIES_STM32H7X)
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP2X)
LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP);
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG1_STOP);
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15 changes: 15 additions & 0 deletions dts/arm/st/mp2/stm32mp2_m33.dtsi
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Expand Up @@ -240,6 +240,21 @@
interrupts = <150 0>;
status = "disabled";
};

iwdg: iwdg4: watchdog@44040000 {
compatible = "st,stm32-watchdog";
reg = <0x44040000 DT_SIZE_K(1)>;
clocks = <&rcc STM32_CLOCK(IWDG4, STM32_CLK)>;
status = "disabled";
};

wwdg: wwdg1: watchdog@44050000 {
compatible = "st,stm32-window-watchdog";
reg = <0x44050000 DT_SIZE_K(1)>;
clocks = <&rcc STM32_CLOCK(WWDG1, STM32_CLK)>;
interrupts = <8 0>;
status = "disabled";
};
};
};

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6 changes: 5 additions & 1 deletion include/zephyr/dt-bindings/clock/stm32mp2_clock.h
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Expand Up @@ -50,7 +50,11 @@
#define STM32_CLOCK_PERIPH_UART8 0x798
#define STM32_CLOCK_PERIPH_UART9 0x79C

/* Watchdog Peripheral */
#define STM32_CLOCK_PERIPH_IWDG4 0x894
#define STM32_CLOCK_PERIPH_WWDG1 0x89C

#define STM32_CLOCK_PERIPH_MIN STM32_CLOCK_PERIPH_GPIOA
#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_UART9
#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_WWDG1

#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ */