stm32mp2: add wwdg1 and iwdg4 support #92319
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Like the H7x series, the MP2x series has a WWDG1 peripheral in the APB3 bus. The MP2 has the same LL function to freeze the watchdog in debug mode. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
Add clock binding for WWDG1 peripheral in STM32MP2 series. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
Add the wwdg1 node, which is the wwdg for non-secure world. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
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WWDG1 clock = ((MCU clock / LSMCU div) /APB3 prescaler) Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
The IWDG4 is on the APB3 bus on STM32MP2x SoCs. When the system is in debug mode, the watchdog should be frozen to prevent it from expiring and resetting the system during debugging sessions. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
Add the IWDG4 clock definition to the STM32MP2 clock bindings. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
This is the independent watchdog for the non-secure world of M33 core. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
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| @@ -72,6 +72,11 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, | |||
| case STM32_CLOCK_PERIPH_UART9: | |||
| *rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE); | |||
| break; | |||
| case STM32_CLOCK_PERIPH_WWDG1: | |||
| /* The WWDG1 clock is derived from the APB3 clock */ | |||
| int wwdg1_clock = 400000000 >> LL_RCC_Get_LSMCUDIVR(); | |||
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Here we should be able to retrieve the frequency instead of hardcoding it.
Seems that it is not implemented in LL.
@erwango : any advice to solve this?
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In STM32 MCU ports, this value comes from DT. So you can put in DT, but it should be somehow sync'ed with A4.
Alternatively, you may have HAL functions to query it.
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This PR adds support for non-secure world M33 watchdogs.
Signed-off-by: Luc BEAUFILS luc.beaufils@savoirfairelinux.com