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stm32mp257f_dk: add m33 support #92316
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stm32mp257f_dk: add m33 support #92316
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minor comments then LGTM
Introduce initial board support for the STM32MP257F-DK Discovery Kit. This includes: - Board metadata (board.yml, stm32mp257f_dk.yaml) - Base software configuration (Kconfig.stm32mp257f_dk) - CMake build integration (board.cmake) - Default configuration (stm32mp257f_dk_stm32mp257fxx_m33_defconfig) - Minimal device tree (stm32mp257f_dk_stm32mp257fxx_m33.dts) - Initial documentation and image for the stm32mp257f_dk board. - OpenOCD configuration files for debugging support. Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
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It seems good to go to me.
Thanks!
- Board connectors: | ||
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- Ethernet RJ45 | ||
- Two stacked USB 2.0 HS Type-A | ||
- USB 3.0 USB Type-C |reg| PD | ||
- microSD |trade| card holder | ||
- Dual-lane MIPI CSI-2 |reg| camera module expansion connector | ||
- HDMI |reg| | ||
- LVDS | ||
- GPIO expansion connector | ||
- VBAT for power backup | ||
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- On-board STLINK-V3EC: | ||
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- Debugger with USB re-enumeration capability: Virtual COM port and debug port | ||
- Board power source through USB Type-C |reg| | ||
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- Mainlined open-source Linux |reg| STM32 MPU OpenSTLinux Distribution and | ||
STM32CubeMP2 software with examples | ||
- Linux |reg| Yocto project |reg|, Buildroot, and STM32CubeIDE as | ||
development environments | ||
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More information about the board can be found at the | ||
`STM32MP257F-DK website`_. | ||
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Hardware | ||
******** | ||
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Cores: | ||
====== | ||
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- 64-bit dual-core Arm |reg| Cortex |reg|-A35 with 1.5 GHz max frequency | ||
- 32-Kbyte I + 32-Kbyte D level 1 cache for each Cortex |reg|-A35 core | ||
- 512-Kbyte unified level 2 cache | ||
- Arm |reg| NEON |trade| and Arm |reg| TrustZone |reg| | ||
- 32-bit Arm |reg| Cortex |reg|-M33 with FPU/MPU, Arm |reg| TrustZone |reg|, | ||
and 400 MHz max frequency | ||
- L1 16-Kbyte ICache / 16-Kbyte DCache for Cortex |reg|-M33 | ||
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Memories: | ||
========= | ||
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- External DDR memory up to 4 Gbytes | ||
- Up to DDR3L-2133 16/32-bit | ||
- Up to DDR4-2400 16/32-bit | ||
- Up to LPDDR4-2400 16/32-bit | ||
- 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or | ||
SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup | ||
domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes in SmartRun domain | ||
- Two Octo-SPI memory interfaces | ||
- Flexible external memory controller with up to 16-bit data bus: parallel | ||
interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC | ||
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Power | ||
===== | ||
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- STPMIC25 for voltage regulation (multiple buck/LDO regulators) | ||
- USB-C power input | ||
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Clock management | ||
================ | ||
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- External oscillators: | ||
- 32.768 kHz LSE crystal | ||
- 40 MHz HSE crystal | ||
- Internal oscillators: | ||
- 64 MHz HSI oscillator | ||
- 4 MHz CSI oscillator | ||
- 32 kHz LSI oscillator | ||
- Five separate PLLs with integer and fractional mode | ||
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Security/Safety | ||
=============== | ||
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- Secure boot, TrustZone |reg| peripherals, active tamper, environmental | ||
monitors, display secure layers, hardware accelerators | ||
- Complete resource isolation framework | ||
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Connectivity | ||
============ | ||
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- 1x Gigabit Ethernet (RGMII) | ||
- USB 2.0 High-Speed Host (dual-port) | ||
- USB Type-C |reg| DRP | ||
- GPIO expansion connector | ||
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Display & Camera | ||
================ | ||
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- LVDS interface (4-lane) | ||
- Camera CSI-2 interface (2-lane) | ||
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Debug | ||
===== | ||
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- STLINK-V3EC (onboard debugger with VCP, JTAG and SWD) | ||
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More information about STM32MP257F can be found here: | ||
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- `STM32MP257F on www.st.com`_ |
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that's three (!) pages of information that really doesn't belong to Zephyr documentation. Please trim it down (and there are some sub-bulllet list that are missing preceding blank line anyway and don't render correctly)
https://builds.zephyrproject.io/zephyr/pr/92316/docs/boards/st/stm32mp257f_dk/doc/index.html
Add the support of this board.
It use the same SoC as the stm32mp257_ev1
Signed-off-by: Luc BEAUFILS luc.beaufils@savoirfairelinux.com