arch: riscv: Add Zc* compressed instruction extension support #92276
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fkokosinski
previously approved these changes
Jun 30, 2025
nordicjm
previously approved these changes
Jun 30, 2025
This commit adds the support for the following new Zc* series compressed instruction extensions: Zca - Subset of the C extension without FP loads and stores Zcb - "Simple" instructions Zcd - Double-precision floating-point instructions Zcf - Single-precision floating-point instructions Zcmp - "Complex" instructions for embedded CPUs Zcmt - Table jump instructions for embedded CPUs With the introduction of the Zc* extensions, the C extension now implies the following Zc* extensions: * Zca, always * Zcf if F is specified (RV32 only) * Zcd if D is specified The Zc* extensions that are implied by the C extension are not specified in the GCC `-march` flag because they are redundant and can interfere with the resolution of the correct multi-lib for the selected architecture unless the the alternate mappings for the redundant forms are manually specified. All the implementation details in this commit are based on the Zc* v1.0.0 specification, which is the ratified version. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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Rebased after #92275 is merged |
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masz-nordic
reviewed
Jul 3, 2025
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| # Zcd is implied by C+D | ||
| if(CONFIG_RISCV_ISA_EXT_ZCD AND | ||
| NOT (CONFIG_RISCV_ISA_EXT_C AND CONFIG_RISCV_ISA_EXT_D)) |
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Checking EXT_D is redundant since zcd depends on EXT_D in Kconfig?
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Technically yes; but, we have nothing to lose by being verbose here.
masz-nordic
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Jul 3, 2025
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Jul 4, 2025
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Includes the commits from #92275Please review the last commit ("arch: riscv: Add Zc* compressed instruction extension support") only.