Rework the I2C driver for the Microchip Polarfire SoC #92208
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area: I2C
platform: Microchip MEC
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@con-pax Would you mind reviewing this MR? |
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Looks pretty good to me, I've not looked in great depth at the changes in the flow using an ISR state machine as I'm not familiar with this hardware, but looked for common things across i2c drivers.
A small nit using k_sem_reset like other drivers rather than a take with no wait.
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teburd
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Clear the clock bits before setting new ones. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Use a mutex to protect the I2C bus from concurrent access. Replace busy waiting with a binary semaphore. Process the messages in the interrupt handler state machine to generate a single transaction. In the interrupt handler, process the states until nothing more is to do. This prevents superfluous interrupt entry/exit pairs. Return error conditions to the caller. Check the messages for consistency and return an error for unsupported message lists. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
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Use a mutex to protect the I2C bus from concurrent access. Replace busy waiting with a binary semaphore. Process the messages in the interrupt handler state machine to generate a single transaction. In the interrupt handler, process the states until nothing more is to do. This prevents superfluous interrupt entry/exit pairs. Return error conditions to the caller. Check the messages for consistency and return an error for unsupported message lists.
The driver was tested using an Icicle development board connected to another board with an I2C target.