arch: riscv: streamline fatal handling code #92104
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`CONFIG_EXTRA_EXCEPTION_INFO` that was added in zephyrproject-rtos#78065 doesn't seem necessary, as we were already storing and printing the callee-saved-registers before that. All `CONFIG_EXTRA_EXCEPTION_INFO` does in RISCV is to add an additional `_callee_saved_t *csf` in the `struct arch_esf`, which overhead is negligible to what's being enabled by `CONFIG_EXCEPTION_DEBUG`. Let's remove `CONFIG_EXTRA_EXCEPTION_INFO`, and have that extra `_callee_saved_t *csf` in the `struct arch_esf` as long as `CONFIG_EXCEPTION_DEBUG` is enabled. Then, since `*csf` is always available in the `struct arch_esf` when `CONFIG_EXCEPTION_DEBUG=y`, we can simply rely on that pointer in `z_riscv_fatal_error()` instead of an additional argument in `z_riscv_fatal_error_csf()`, rendering it redundant and thus can be removed. Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com> Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Refactor the csf saving code into a macro and calls it before jumping to `z_riscv_fault()`, so that callee-saved-registers are printed on generic CPU exception as well. Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com> Signed-off-by: Yong Cong Sin <ycsin@meta.com>
- Updated the testcase to test `z_riscv_fault()` error handling path. - The main file is now fully assembly so that we can use precompiler guards more easily to test with/without frame pointer enabled. Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com> Signed-off-by: Yong Cong Sin <ycsin@meta.com>
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Note
This is the recreation of #81688