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tests: arch: riscv: fatal: test z_riscv_fault() path
- Updated the testcase to test `z_riscv_fault()` error handling path. - The main file is now fully assembly so that we can use precompiler guards more easily to test with/without frame pointer enabled. Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com> Signed-off-by: Yong Cong Sin <ycsin@meta.com>
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5 files changed

+174
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lines changed

‎tests/arch/riscv/fatal/CMakeLists.txt

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@@ -4,5 +4,5 @@ cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(riscv_fatal)
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7-
FILE(GLOB app_sources src/*.c)
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FILE(GLOB app_sources src/*.S)
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target_sources(app PRIVATE ${app_sources})

‎tests/arch/riscv/fatal/Kconfig

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# Copyright (c) 2024 Meta Platforms
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Fatal type"
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default TEST_RISCV_FATAL_PANIC
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config TEST_RISCV_FATAL_PANIC
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bool "Panic induced fault"
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help
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Tests the error handling via `z_riscv_fatal_error()`
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config TEST_RISCV_FATAL_ILLEGAL_INSTRUCTION
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bool "Illegal instruction induced fault"
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help
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Tests the error handling via `_Fault()`
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endchoice
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source "Kconfig.zephyr"

‎tests/arch/riscv/fatal/src/main.S

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/*
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* Copyright (c) 2025 Meta Platforms.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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/**
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* Load up a bunch of known values into registers
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* and expect them to show up in the core dump.
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* Value is register ABI name kinda spelled out,
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* followed by zeros to pad to 32 bits,
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* followed by FF00, followed by hex number of the register,
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* follwed by the "hex-coded-decimal" number of the register.
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*/
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GTEXT(main)
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SECTION_FUNC(TEXT, main)
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li ra, 0xDADA0000FF000101
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/* SP is skipped because it can messes stuff up */
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#ifndef CONFIG_RISCV_GP
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li gp, 0xDADA0000FF000101
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#endif
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#ifndef CONFIG_THREAD_LOCAL_STORAGE
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li tp, 0xE2E20000FF000404
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#endif /* CONFIG_THREAD_LOCAL_STORAGE */
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#ifndef CONFIG_TEST_RISCV_FATAL_PANIC
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/* We will load `0` (RV_ECALL_RUNTIME_EXCEPT) to `t0` */
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li t0, 0xD0FF0000FF000505
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#endif /* CONFIG_TEST_RISCV_FATAL_PANIC */
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li t1, 0xD1FF0000FF000606
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li t2, 0xD2FF0000FF000707
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#ifndef CONFIG_FRAME_POINTER
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li s0, 0xC0FF0000FF000808
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#endif /* CONFIG_FRAME_POINTER */
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li s1, 0xC1FF0000FF000909
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li a0, 0xA0FF0000FF000A10
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li a1, 0xA1FF0000FF000B11
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li a2, 0xA2FF0000FF000C12
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li a3, 0xA3FF0000FF000D13
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li a4, 0xA4FF0000FF000E14
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li a5, 0xA5FF0000FF000F15
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#ifndef CONFIG_RISCV_ISA_RV32E
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li a6, 0xA6FF0000FF001016
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li a7, 0xA7FF0000FF001117
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li s2, 0xC2FF0000FF001218
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li s3, 0xC3FF0000FF001319
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li s4, 0xC4FF0000FF001420
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li s5, 0xC5FF0000FF001521
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li s6, 0xC6FF0000FF001622
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li s7, 0xC7FF0000FF001723
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li s8, 0xC8FF0000FF001824
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li s9, 0xC9FF0000FF001925
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li s10, 0xC10FF000FF001A26
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li s11, 0xC11FF000FF001B27
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li t3, 0xD3FF0000FF001C28
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li t4, 0xD4FF0000FF001D29
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li t5, 0xD5FF0000FF001E30
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li t6, 0xD6FF0000FF001F31
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#endif /* CONFIG_RISCV_ISA_RV32E */
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#ifdef CONFIG_TEST_RISCV_FATAL_PANIC
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li a0, 4 /* K_ERR_KERNEL_PANIC */
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li t0, 0 /* RV_ECALL_RUNTIME_EXCEPT */
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ecall
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#else /* CONFIG_TEST_RISCV_FATAL_ILLEGAL_INSTRUCTION */
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.insn 2, 0
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.insn 2, 0
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#endif /* CONFIG_TEST_RISCV_FATAL_PANIC */

‎tests/arch/riscv/fatal/src/main.c

Lines changed: 0 additions & 62 deletions
This file was deleted.

‎tests/arch/riscv/fatal/testcase.yaml

Lines changed: 70 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,10 @@ common:
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platform_allow:
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- qemu_riscv64
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tests:
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arch.riscv64.fatal:
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arch.riscv64.fatal.panic_sp:
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extra_configs:
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- CONFIG_FRAME_POINTER=n
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- CONFIG_TEST_RISCV_FATAL_PANIC=y
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harness_config:
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type: multi_line
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regex:
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- "E: s3: c3ff0000ff001319 s9: c9ff0000ff001925"
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- "E: s4: c4ff0000ff001420 s10: c10ff000ff001a26"
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- "E: s5: c5ff0000ff001521 s11: c11ff000ff001b27"
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arch.riscv64.fatal.fault_sp:
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extra_configs:
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- CONFIG_FRAME_POINTER=n
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- CONFIG_TEST_RISCV_FATAL_ILLEGAL_INSTRUCTION=y
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harness_config:
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type: multi_line
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regex:
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- "E: a0: a0ff0000ff000a10 t0: d0ff0000ff000505"
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- "E: a1: a1ff0000ff000b11 t1: d1ff0000ff000606"
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- "E: a2: a2ff0000ff000c12 t2: d2ff0000ff000707"
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- "E: a3: a3ff0000ff000d13 t3: d3ff0000ff001c28"
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- "E: a4: a4ff0000ff000e14 t4: d4ff0000ff001d29"
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- "E: a5: a5ff0000ff000f15 t5: d5ff0000ff001e30"
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- "E: a6: a6ff0000ff001016 t6: d6ff0000ff001f31"
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- "E: a7: a7ff0000ff001117"
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- "E: ra: dada0000ff000101"
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- "E: s0: c0ff0000ff000808 s6: c6ff0000ff001622"
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- "E: s1: c1ff0000ff000909 s7: c7ff0000ff001723"
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- "E: s2: c2ff0000ff001218 s8: c8ff0000ff001824"
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- "E: s3: c3ff0000ff001319 s9: c9ff0000ff001925"
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- "E: s4: c4ff0000ff001420 s10: c10ff000ff001a26"
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- "E: s5: c5ff0000ff001521 s11: c11ff000ff001b27"
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arch.riscv64.fatal.panic_fp:
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extra_configs:
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- CONFIG_FRAME_POINTER=y
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- CONFIG_TEST_RISCV_FATAL_PANIC=y
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harness_config:
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type: multi_line
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regex:
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- "E: a0: 0000000000000004 t0: 0000000000000000"
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- "E: a1: a1ff0000ff000b11 t1: d1ff0000ff000606"
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- "E: a2: a2ff0000ff000c12 t2: d2ff0000ff000707"
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- "E: a3: a3ff0000ff000d13 t3: d3ff0000ff001c28"
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- "E: a4: a4ff0000ff000e14 t4: d4ff0000ff001d29"
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- "E: a5: a5ff0000ff000f15 t5: d5ff0000ff001e30"
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- "E: a6: a6ff0000ff001016 t6: d6ff0000ff001f31"
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- "E: a7: a7ff0000ff001117"
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- "E: ra: dada0000ff000101"
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- "E: s0: \\w+ s6: c6ff0000ff001622"
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- "E: s1: c1ff0000ff000909 s7: c7ff0000ff001723"
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- "E: s2: c2ff0000ff001218 s8: c8ff0000ff001824"
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- "E: s3: c3ff0000ff001319 s9: c9ff0000ff001925"
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- "E: s4: c4ff0000ff001420 s10: c10ff000ff001a26"
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- "E: s5: c5ff0000ff001521 s11: c11ff000ff001b27"
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arch.riscv64.fatal.fault_fp:
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extra_configs:
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- CONFIG_FRAME_POINTER=y
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- CONFIG_TEST_RISCV_FATAL_ILLEGAL_INSTRUCTION=y
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harness_config:
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type: multi_line
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regex:
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- "E: a0: a0ff0000ff000a10 t0: d0ff0000ff000505"
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- "E: a1: a1ff0000ff000b11 t1: d1ff0000ff000606"
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- "E: a2: a2ff0000ff000c12 t2: d2ff0000ff000707"
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- "E: a3: a3ff0000ff000d13 t3: d3ff0000ff001c28"
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- "E: a4: a4ff0000ff000e14 t4: d4ff0000ff001d29"
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- "E: a5: a5ff0000ff000f15 t5: d5ff0000ff001e30"
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- "E: a6: a6ff0000ff001016 t6: d6ff0000ff001f31"
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- "E: a7: a7ff0000ff001117"
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- "E: ra: dada0000ff000101"
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- "E: s0: \\w+ s6: c6ff0000ff001622"
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- "E: s1: c1ff0000ff000909 s7: c7ff0000ff001723"
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- "E: s2: c2ff0000ff001218 s8: c8ff0000ff001824"
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- "E: s3: c3ff0000ff001319 s9: c9ff0000ff001925"
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- "E: s4: c4ff0000ff001420 s10: c10ff000ff001a26"
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- "E: s5: c5ff0000ff001521 s11: c11ff000ff001b27"

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