drivers: spi: spi_max32: Fix word size support #92027
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@vladislav-pejic @dimitrije-lilic can you test this with RTIO?
| @@ -103,7 +103,7 @@ static int spi_configure(const struct device *dev, const struct spi_config *conf | |||
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| ret = Wrap_MXC_SPI_Init(regs, master_mode, quad_mode, num_slaves, ss_polarity, spi_speed); | |||
| if (ret) { | |||
| return ret; | |||
| return -EINVAL; | |||
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could you make a different commit for fixing the error codes ?
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Updated the copyright dates in |
@MaureenHelm We have tested this fix with RTIO for AD4052 and ADXL367 and in both cases RTIO SPI is not working. Functions for RTIO SPI were not updated and are still using old shifts. We used sample.sensor.accel_polling.adxl367-stream test for ADXL367 and sample.driver.adc_stream.ad4052-stream for AD4052 (from this PR #90285). |
I have added the necessary fixes for the RTIO part, and tests succeed on my setup. However, I do not have an ADXL367 with me at the moment so is it possible for you to try again? Thanks. |
We run the tests again and results are the same. RTIO SPI is still not working with both chips. When chips are initializing, first SPI read for device id and part id returns wrong values (0xc0 and 0xc0 for ADXL367, 0xff and 0xff for AD4052). |
Driver was not handling SPI word sizes other than 8 bits. Apply DFS shift wherever necessary to support non 8-bit transfers. DMA mode cannot support word sizes that are less than 8 bits so return -ENOTSUP if word size less than 8-bits is required. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
spi_configure was returning HAL error codes that are incompatible with Zephyr error definitions straight back to the caller. Replace these with error codes that Zephyr can correctly interpret. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The requested SPI clock rate and the actual rate that is set can be different depending on the peripheral clock and divisors available to the SPI peripheral. For some MAX32 SoCs, actual rate ended up being higher than the devicetree setting. This would then cause latency tests to fail as transfers finish earlier than minimum expected duration. Update the test frequency values in several MAX32 board overlays to pass latency tests. Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
I believe I have sorted it out now. Still trying to find an ADXL367 to verify. |
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@vladislav-pejic @dimitrije-lilic can you test this with RTIO?
@MaureenHelm We have tested this fix with RTIO for AD4052 and ADXL367 and in both cases RTIO SPI is not working. Functions for RTIO SPI were not updated and are still using old shifts. We used sample.sensor.accel_polling.adxl367-stream test for ADXL367 and sample.driver.adc_stream.ad4052-stream for AD4052 (from this PR #90285).
I have added the necessary fixes for the RTIO part, and tests succeed on my setup. However, I do not have an ADXL367 with me at the moment so is it possible for you to try again? Thanks.
We run the tests again and results are the same. RTIO SPI is still not working with both chips. When chips are initializing, first SPI read for device id and part id returns wrong values (0xc0 and 0xc0 for ADXL367, 0xff and 0xff for AD4052).
I believe I have sorted it out now. Still trying to find an ADXL367 to verify.
I tested sample.sensor.accel_polling.adxl345-stream and it works well.
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Tested the |
danieldegrasse
added
the
backport-v4.2-branch
Recent updates to SPI loopback tests (https://github.com/zephyrproject-rtos/zephyr/commits/main/tests/drivers/spi/spi_loopback/src?since=2025-03-21&until=2025-06-23) uncovered a few bugs in the MAX32 SPI driver, mostly related to word size handling.
Fix the driver so that SPI word lengths other than 8-bits are properly handled. Return
-ENOTSUPif the requested word length is not supported.A couple of other fixes:
test_spi_complete_multiple_timedtest.test_nop_nil_bufsandtest_spi_null_tx_rx_buf_set.Before:
After: