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soc: rp2350: Add basic Asymmetric Multiprocessing (AMP) support #90922
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The CI error message:
It looks like C language features used in RPi SDK are getting in the way. |
Hopefully patch in #90939 help fix the tests! |
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just some thoughts
type: mcu | ||
arch: arm | ||
flash: 4096 | ||
ram: 520 | ||
ram: 264 |
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type: mcu | ||
arch: arm | ||
flash: 4096 | ||
ram: 264 |
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@@ -17,4 +17,10 @@ config RPI_PICO_ROSC_USE_MEASURED_FREQ | |||
Instead of the dts value, use the value measured by | |||
the frequency counter as the rosc frequency. | |||
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config RPI_PICO_SKIP_CLOCK_INIT |
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Perhaps needs some more DT-centric approach as I've discussed in Discord
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Because there are other parts like clock and reset controllers for peripherals
This commit introduces a means to build Zephyr for both Cortex M33 cores of the RP2350, and for CPU0 to boot CPU1. It includes a partition table for the rpi_pico2 board that demonstrates how the two cores can operate independently. Signed-off-by: Dan Collins <dan@collinsnz.com>
We don't want to reinitialise the clock control when we boot the second core - so this commit introduces a means to skip initialisation (i.e. assume it is already initialised). Signed-off-by: Dan Collins <dan@collinsnz.com>
This commit introduces an interprocess mailbox driver for the Raspberry Pi Pico. Signed-off-by: Dan Collins <dan@collinsnz.com>
I have split this out into three commits for now - this makes it easier to track what's going on. I've also removed the changes to the various samples/tests as I really like @dsseng's idea to avoid forcing the I also like the idea of using the device tree for disabling the clock init, rather than the Kconfig symbol I have. I'm not sure how to do that exactly - whether it's a special compat for the second core, or just a flag. |
As we discussed with @dancollins on Discord, I'll do some work, including implementing my proposed changes and perhaps IPM on my branch and notify here when some major progress is there |
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I have a project using the RP2350, and figured it would be cool to run Zephyr on both cores. I have got a basic sample working that has both cores running Zephyr and printing a message on their respective UARTs.
I have noticed the reset controller, as an example, makes use of read-modify-writes that will not be compatible with my AMP setup. This, along with other peripherals, will need to either have hardware locking (RP2350 includes a hardware spinlock) or atomic access (RP2350 has memory addresses for atomic set/clear).
No doubt issues will crop up as I use this implementation - so I will keep it in draft status until I stop needing to make any changes to it. I intend on being able to demonstrate an OpenAMP sample running, as this should provide all the basic functionality needed for AMP.