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Add support for WCH CH32L103 #89451

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f8a4e2d
drivers: clock_control: Add fix to wch clock control for ch32l103
paulwedeck May 4, 2025
855059c
soc: Introduce WCH CH32L103 SoC
paulwedeck May 4, 2025
eeb0341
boards: add ch32l103evt board
paulwedeck May 4, 2025
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67 changes: 67 additions & 0 deletions dts/riscv/wch/ch32l103/ch32l103.dtsi
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/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <wch/ch32v208/ch32v208.dtsi>


/ {
soc {
dma1: dma@40020000 {
compatible = "wch,wch-dma";
reg = <0x40020000 0x90>;
clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>;
#dma-cells = <1>;
interrupt-parent = <&pfic>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>, <62>;
dma-channels = <8>;
};
};
};

&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
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The HSE frequency depends on the crystal on the board, so move this out to the board definition.

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The reason why I set it here is because ch32v208.dtsi sets it to a value larger than is supported by the l103.
The board uses a 8MHz crystal and sets the correct frequency in the board dts, so this rather marks the max value instead of the actual value.
Is is this a valid reasoning (for zephyr) or should I remove this part?

};

&clk_lsi {
clock-frequency = <DT_FREQ_K(40)>;
};

&sram0 {
reg = <0x20000000 DT_SIZE_K(20)>;
};

&flash {
reg = <0x40022000 0x28>;
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This is very similar to the definition in ch32v208.dtsi. Is the included file wrong? If so, should this fix be there?

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You are right, this was already wrong for the v208. Should I include a commit here or add a separate pr?

};

&flash0 {
reg = <0 DT_SIZE_K(64)>;
};

&gpioa {
ngpios = <16>;
};

&gpiob {
ngpios = <16>;
};

&gpioc {
gpio-reserved-ranges = <0 13>;
ngpios = <16>;
};

&gpiod {
ngpios = <2>;
};

&usart4 {
interrupts = <61>;
};

&cpu0 {
clock-frequency = <DT_FREQ_M(96)>;
};
7 changes: 7 additions & 0 deletions dts/riscv/wch/ch32l103/ch32l103c8t.dtsi
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/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <wch/ch32l103/ch32l103.dtsi>
15 changes: 15 additions & 0 deletions dts/riscv/wch/ch32l103/ch32l103f8p.dtsi
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/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <wch/ch32l103/ch32l103.dtsi>

&gpioa {
gpio-reserved-ranges = <9, 3>, <15, 1>;
};

&gpiob {
gpio-reserved-ranges = <0, 1>, <2, 4>, <9, 7>;
};
15 changes: 15 additions & 0 deletions dts/riscv/wch/ch32l103/ch32l103f8u.dtsi
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/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <wch/ch32l103/ch32l103.dtsi>

&gpioa {
gpio-reserved-ranges = <15, 1>;
};

&gpiob {
gpio-reserved-ranges = <2, 4>, <8, 2>, <12, 1>;
};
15 changes: 15 additions & 0 deletions dts/riscv/wch/ch32l103/ch32l103g8r.dtsi
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/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <wch/ch32l103/ch32l103.dtsi>

&gpioa {
gpio-reserved-ranges = <15, 1>;
};

&gpiob {
gpio-reserved-ranges = <2, 1>, <4, 1>, <9, 1>;
};
11 changes: 11 additions & 0 deletions dts/riscv/wch/ch32l103/ch32l103k8u.dtsi
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/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <wch/ch32l103/ch32l103.dtsi>

&gpiob {
gpio-reserved-ranges = <10, 5>;
};
12 changes: 12 additions & 0 deletions soc/wch/ch32v/qingke_v4c/Kconfig.defconfig.ch32l103
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# Copyright (c) 2025 Paul Wedeck
# SPDX-License-Identifier: Apache-2.0

if SOC_CH32L103

config VECTOR_TABLE_SIZE
default 68

config NUM_IRQS
default 128

endif # SOC_CH32L103
9 changes: 9 additions & 0 deletions soc/wch/ch32v/qingke_v4c/Kconfig.soc.ch32l103
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# Copyright (c) 2025 Paul Wedeck
# SPDX-License-Identifier: Apache-2.0

config SOC_CH32L103
bool
select SOC_SERIES_QINGKE_V4C

config SOC
default "ch32l103" if SOC_CH32L103
1 change: 1 addition & 0 deletions soc/wch/ch32v/soc.yml
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Expand Up @@ -10,3 +10,4 @@ family:
- name: qingke-v4c
socs:
- name: ch32v208
- name: ch32l103