Add support for WCH CH32L103

boards/wch/ch32l103evt/Kconfig.ch32l103evt

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Paul Wedeck
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CH32L103EVT
+	select SOC_CH32L103

boards/wch/ch32l103evt/board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(minichlink)
+include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake)

boards/wch/ch32l103evt/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: ch32l103evt
+  full_name: WCH CH32L103C8T6-R0-1v2
+  vendor: wch
+  socs:
+    - name: ch32l103

boards/wch/ch32l103evt/ch32l103evt-pinctrl.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Michael Hope <michaelh@juju.nz>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h>
+
+&pinctrl {
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <USART1_TX_PA9_0>;
+			output-high;
+			drive-push-pull;
+			slew-rate = "max-speed-10mhz";
+		};
+		group2 {
+			pinmux = <USART1_RX_PA10_0>;
+			bias-pull-up;
+		};
+	};
+};

boards/wch/ch32l103evt/ch32l103evt.dts

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2024 Michael Hope <michaelh@juju.nz>
+ * Copyright (c) 2025 Paul Wedeck
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <wch/ch32l103/ch32l103c8t.dtsi>
+#include "ch32l103evt-pinctrl.dtsi"
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "ch32l103evt";
+	compatible = "wch,ch32l103";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * Please connect the unconnected LED on the WCH CH32L103EVT
+		 * board to a suitable GPIO pin (like PA1) and then change
+		 * this status to "okay".
+		 */
+		status = "disabled";
+
+		red_led: led0 {
+			gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	aliases {
+		led0 = &red_led;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(8)>;
+	status = "okay";
+};
+
+&pll {
+	clocks = <&clk_hse>;
+	mul = <12>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&usart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};

boards/wch/ch32l103evt/ch32l103evt.yaml

@@ -0,0 +1,12 @@
+identifier: ch32l103evt
+name: WCH CH32L103C8T6-R0-1v2
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 64
+flash: 20
+supported:
+  - gpio
+  - dma

boards/wch/ch32l103evt/ch32l103evt_defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/wch/ch32l103evt/doc/index.rst

@@ -0,0 +1,88 @@
+.. zephyr:board:: ch32l103evt
+
+Overview
+********
+
+The `WCH`_ CH32L103EVT hardware provides support for QingKe 32-bit RISC-V4C
+processor and the following devices:
+
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`DMA (Direct Memory Access)`
+
+The board is equipped with two LEDs.
+The `WCH webpage on CH32L103`_ contains the processor's manuals.
+The `WCH webpage on CH32L103EVT`_ contains the CH32L103EVT's schematic.
+
+Hardware
+********
+
+The QingKe 32-bit RISC-V4C processor of the WCH CH32L103EVT is clocked by an external
+8 MHz crystal or the internal 8 MHz oscillator and runs up to 96 MHz.
+The CH32V208 SoC Features 4 USART, 4 GPIO ports, 2 SPI, 2 I2C, ADC, RTC,
+CAN FD, USB 2.0 Host, USB Type-C PD, OPA, and  several timers.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+LED
+---
+
+* LED3/LED4 = Unconnected. Connect to an I/O pin (PA1).
+
+Button
+------
+
+* S1 = Reset Button
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``CH32L103EVT`` board target can be built and flashed
+in the usual way (see :ref:`build_an_application` and :ref:`application_run`
+for more details); however, an external programmer is required since the board
+does not have any built-in debug support.
+
+The following pins of the external programmer must be connected to the
+following pins on the PCB:
+
+* VCC = VCC
+* GND = GND
+* SWIO = PA13
+* SWCLK = PA14
+
+Flashing
+========
+
+You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set
+up, build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ch32l103evt
+   :goals: build flash
+
+Debugging
+=========
+
+This board can be debugged via ``minichlink``.
+
+References
+**********
+
+.. target-notes::
+
+.. _WCH: http://www.wch-ic.com
+.. _WCH webpage on CH32L103: https://www.wch-ic.com/products/CH32L103.html
+.. _WCH webpage on CH32L103EVT: https://www.wch.cn/downloads/CH32L103EVT_ZIP.html

boards/wch/ch32l103evt/support/openocd.cfg

@@ -0,0 +1,15 @@
+#interface wlink
+adapter driver wlink
+wlink_set
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"

drivers/clock_control/clock_control_wch_rcc.c

@@ -132,6 +132,16 @@
 		}
 	}
 
+#if defined(CONFIG_SOC_CH32L103)
+	if(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 72*1000*1000) {
+		FLASH->ACTLR = 2;
+	} else if(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 40*1000*1000) {
+		FLASH->ACTLR = 1;
+	} else {
+		FLASH->ACTLR = 0;
+	}
+#endif
+
 	if (IS_ENABLED(WCH_RCC_SRC_IS_HSI)) {
 		RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI;
 	} else if (IS_ENABLED(WCH_RCC_SRC_IS_HSE)) {

dts/riscv/wch/ch32l103/ch32l103.dtsi

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 Paul Wedeck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v208/ch32v208.dtsi>
+
+
+/ {
+	soc {
+		dma1: dma@40020000 {
+			compatible = "wch,wch-dma";
+			reg = <0x40020000 0x90>;
+			clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>;
+			#dma-cells = <1>;
+			interrupt-parent = <&pfic>;
+			interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>, <62>;
+			dma-channels = <8>;
+		};
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(25)>;
+};
+
+&clk_lsi {
+	clock-frequency = <DT_FREQ_K(40)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(20)>;
+};
+
+&flash {
+	reg = <0x40022000 0x28>;
+};
+
+&flash0 {
+	reg = <0 DT_SIZE_K(64)>;
+};
+
+&gpioa {
+	ngpios = <16>;
+};
+
+&gpiob {
+	ngpios = <16>;
+};
+
+&gpioc {
+	gpio-reserved-ranges = <0 13>;
+	ngpios = <16>;
+};
+
+&gpiod {
+	ngpios = <2>;
+};
+
+&usart4 {
+	interrupts = <61>;
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(96)>;
+};

dts/riscv/wch/ch32l103/ch32l103c8t.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Paul Wedeck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32l103/ch32l103.dtsi>

dts/riscv/wch/ch32l103/ch32l103f8p.dtsi

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Paul Wedeck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32l103/ch32l103.dtsi>
+
+&gpioa {
+        gpio-reserved-ranges = <9, 3>, <15, 1>;
+};
+
+&gpiob {
+        gpio-reserved-ranges = <0, 1>, <2, 4>, <9, 7>;
+};

dts/riscv/wch/ch32l103/ch32l103f8u.dtsi

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Paul Wedeck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32l103/ch32l103.dtsi>
+
+&gpioa {
+        gpio-reserved-ranges = <15, 1>;
+};
+
+&gpiob {
+        gpio-reserved-ranges = <2, 4>, <8, 2>, <12, 1>;
+};

dts/riscv/wch/ch32l103/ch32l103g8r.dtsi

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Paul Wedeck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32l103/ch32l103.dtsi>
+
+&gpioa {
+        gpio-reserved-ranges = <15, 1>;
+};
+
+&gpiob {
+        gpio-reserved-ranges = <2, 1>, <4, 1>, <9, 1>;
+};