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Flexio SPI loopback test failed on fast speed(16Mbps) #88877

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Merged
merged 2 commits into from
Jun 27, 2025
Merged

Flexio SPI loopback test failed on fast speed(16Mbps) #88877

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dea6daa
drivers: spi: nxp: flexiospi spi_loopback test failed on flexio spi
Raymond0225 Apr 18, 2025
bf028ef
test: spi_loopback: nxp: Add Flexio spi test support
Raymond0225 Apr 21, 2025
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7 changes: 2 additions & 5 deletions drivers/clock_control/clock_control_mcux_ccm_rev2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -225,11 +225,8 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
#endif

#ifdef CONFIG_MCUX_FLEXIO
case IMX_CCM_FLEXIO1_CLK:
clock_root = kCLOCK_Root_Flexio1;
break;
case IMX_CCM_FLEXIO2_CLK:
clock_root = kCLOCK_Root_Flexio2;
case IMX_CCM_FLEXIO_CLK:
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I don't see this defined in include/zephyr/dt-bindings/clock/imx_ccm_rev2.h. You also need to update the dts file where this is used i.e: ./dts/arm/nxp/nxp_rt11xx.dtsi

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I don't see this defined in include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
what do you mean?

I found below in imx_ccm_rev2.h
/* FLEXIO */
#define IMX_CCM_FLEXIO_CLK 0x1700UL
#define IMX_CCM_FLEXIO1_CLK 0x1700UL
#define IMX_CCM_FLEXIO2_CLK 0x1701UL

clock_root = kCLOCK_Root_Flexio1 + instance;
break;
#endif

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18 changes: 18 additions & 0 deletions drivers/spi/spi_mcux_flexio.c
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Expand Up @@ -206,6 +206,24 @@ static void spi_flexio_master_init(FLEXIO_SPI_Type *base, flexio_spi_master_conf
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
/* Low 8-bits are used to configure baudrate. */
timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps);

/* Add protection if the required band rate overflows.
* FLEXIO input freq can't meet required band rate. Max band rate can
* not exceed 1/4 of input freq. You can raise input freq or lower
* bandrate required to remove this warning.
*/
if (timerDiv < 4) {
timerDiv = 4;
}
/* If timeDiv is odd, get it to even. */
timerDiv += timerDiv & 1UL;

if (masterConfig->baudRate_Bps != (srcClock_Hz / timerDiv)) {
LOG_WRN("Bandrate req:%uKbps, got:%uKbps",
(uint32_t)(masterConfig->baudRate_Bps / 1000),
(uint32_t)(srcClock_Hz / (timerDiv*1000)));
}

timerDiv = timerDiv / 2U - 1U;
/* High 8-bits are used to configure shift clock edges(transfer width). */
timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U;
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12 changes: 12 additions & 0 deletions soc/nxp/imxrt/imxrt10xx/soc.c
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Expand Up @@ -215,6 +215,18 @@ __weak void clock_init(void)
CLOCK_SetDiv(kCLOCK_LpspiDiv, 0); /* Set SPI divider to 1 */
#endif

#ifdef CONFIG_MCUX_FLEXIO
/* Configure input clock to be able to reach the datasheet specified baud rate.
* FLEXIO can reach to 120MHz. Select USB pll(480M) as source and divide by 2.
* pre divider by default is 1 which means divide by 2.
*/
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
CLOCK_SetDiv(kCLOCK_Flexio1Div, 1);

CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
CLOCK_SetDiv(kCLOCK_Flexio2Div, 1);
#endif

#ifdef CONFIG_DISPLAY_MCUX_ELCDIF
/* MUX selects video PLL, which is initialized to 93MHz */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
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12 changes: 12 additions & 0 deletions soc/nxp/imxrt/imxrt11xx/soc.c
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Expand Up @@ -391,6 +391,18 @@ __weak void clock_init(void)
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
#endif

#ifdef CONFIG_MCUX_FLEXIO
/* Configure flexio1 with oscRC400M */
rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);

/* Configure flexio2 using oscRC400M */
rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
#endif

#ifdef CONFIG_I2C_MCUX_LPI2C
/* Configure Lpi2c1 using Osc48MDiv2 */
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
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