drivers: ethernet: Add Intel® i226 Ethernet Controller Driver #88108

Vijayakannan · 2025-04-03T12:24:06Z

The Intel i226 Ethernet Controller is a PCIe Gen 2 one-lane modular endpoint device that integrates a fully featured GbE Media Access Control (MAC) and Physical Layer (PHY) port. This PR introduces a complete driver bundle to enable Intel i226 Ethernet Controller.

**Components: **

MAC Driver, MDIO Driver & Parent Platform Driver

**Features Supported: **

Full duplex support for 10/100/1000 Mbps.
Half duplex support for 10/100 Mbps.
MSI-X interrupt support for TX/RX DMA channels.
Exclusive bottom-half processing for each hardware queue.
Auto-Negotiation for 10/100/1000 Mbps.
MTU customization for flexible packet sizes.
MAC address filtering support for:
- Random MAC Address Generated.
- MAC addresses specified in the device tree.
- Pre-programmed MAC addresses in EEPROM.
MDIO Clause 22 (C22) and Clause 45 (C45) support.
Multi-instance support to scale the system. (Tested Up to 2 instances with basic coverage)

**Other Notes: **

The Parent Platform Driver is designed to be modular and reusable for other PCIe-based Ethernet devices.
2.5 Gbps, Time Sync and other TSN features were not enabled despite the hardware having support.

**Validation Coverage: **
This driver bundle has been tested on Intel Alder Lake platforms with the Intel i226 LM variant Ethernet Controller(0x125B). The ZPERF network sample application was used to validate basic functionality, performance, and stability.

Test List:

Transmit and receive UDP packet,
Transmit and receive TCP packet,
Speed: 10/100/1000Mbps, Duplex: Full, Auto-negotiation: ON,
Speed: 10/100; Duplex: Half/Full, Auto-negotiation: ON,
Speed: 10/100/1000Mbps, Duplex: Full, Auto-negotiation: ON (set_link in net shell),
Speed: 10/100Mbps, Duplex: Half, Auto-negotiation: ON (set_link in net shell),
TX and RX with different MTU sizes: 256, 512, and 1024
Throughput KPI for UDP upload and download (100/1000 Mbps),
Latency KPI: 100 Mbps, 500 us packet interval with 500,1500 bytes packet size,
Latency KPI: 1000 Mbps, 125 us packet interval, 200 bytes packet size,
Ethernet Cable hot-plug with different number of hardware queues.
MDIO Clause - 22/45 Support,
Configure MAC address via net shell,
Configure local MAC address via device tree,

github-actions · 2025-04-03T12:24:48Z

Hello @Vijayakannan, and thank you very much for your first pull request to the Zephyr project!
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maass-hamburg · 2025-04-03T16:45:25Z

On a first look:

the Link status change detection should happen in the phy. we have the phy_link_callback_set() to set a callback function in the phy from the mac. In that callback net_eth_carrier_on() and net_eth_carrier_off() should be called.
It's generall best to not have code for the phy in the ethernet driver. It's preferd if the official zephyr apis are used for communication between the phy and mac driver.

Vijayakannan · 2025-04-04T06:19:36Z

On a first look:

Hi Fin Maaß, Thanks for spending time to review and recommendations.

the Link status change detection should happen in the phy. we have the phy_link_callback_set() to set a callback function in the phy from the mac. In that callback net_eth_carrier_on() and net_eth_carrier_off() should be called.

It's generall best to not have code for the phy in the ethernet driver. It's preferd if the official zephyr apis are used for communication between the phy and mac driver.

I agree with your suggestions and work on it.

Rationale on why earlier decided to use MAC for Link detection:
Intel i226 integrates the GbE MAC and PHY into a single chip. Additionally, MAC includes automatic Link detection functionality and update its registers automatically, which simplifies usage. So, in my initial design opted to handle it directly in MAC to avoid the overhead of invoking PHY-to-MAC callback.

I am open for your suggestion in case if you have other thoughts. - Thanks, Vijay

drivers/ethernet/phy/phy_intel_igc.c

drivers/mdio/mdio_intel_igc.c

Vijayakannan · 2025-04-23T06:10:30Z

On a first look:

Hi Fin Maaß, Thanks for spending time to review and recommendations.

the Link status change detection should happen in the phy. we have the phy_link_callback_set() to set a callback function in the phy from the mac. In that callback net_eth_carrier_on() and net_eth_carrier_off() should be called.

It's generall best to not have code for the phy in the ethernet driver. It's preferd if the official zephyr apis are used for communication between the phy and mac driver.

I agree with your suggestions and work on it.

Progress Update:
The interrupt line used for this PHY link status change is shared for multiple purposes as per the hardware design. Therefore, I have started a small refactor to accommodate this review comment and all other use cases. Let me publish the changes once I finish my sanity checks.

Vijayakannan · 2025-07-02T17:44:49Z

Hi All,

Please review the updated PR version 6 and share your feedback. Thanks in advance, Vijay

Changes since v5:

Apply Clang format to MDIO, PHY, MAC, and platform driver sources for consistent code style.
Remove phy_intel_igc_await_phy_status.
Remove phy_intel_igc_aneg_10_100mbps.
Remove phy_intel_igc_aneg_1000mbps.
Remove phy_intel_igc_restart_aneg.
Use the common phy_mii_cfg_link_autoneg instead of the custom phy_intel_igc_cfg_link.
Optimize phy_intel_igc_init.
Add a default speed generation macro, referencing the implementation in the phy_mii.c driver.
Added the list of test cases as part this PR description to qualify this driver bundle.

Vijayakannan · 2025-07-04T04:20:16Z

Hi @maass-hamburg, please approve if there are no more comments from your side.

Vijayakannan · 2025-07-10T03:01:09Z

Hi @maass-hamburg, please approve if there are no more comments from your side.

Hi @maass-hamburg, just a reminder to add this PR in your review list. Thanks in advance.

maass-hamburg · 2025-07-10T06:58:13Z

@Vijayakannan I'm still not happy about the phy irq in the eth driver and not being in the platform driver.
But we could shorten it here and you can just for now use the generic ethernet-phy driver and add your specific phy driver with the correct irq handling later.

Vijayakannan · 2025-07-10T08:40:45Z

@Vijayakannan I'm still not happy about the phy irq in the eth driver and not being in the platform driver. But we could shorten it here and you can just for now use the generic ethernet-phy driver and add your specific phy driver with the correct irq handling later.

sure. I have replied to the earlier review comment to keep track of this discussion.

drivers/ethernet/intel/eth_intel_igc.c

Vijayakannan · 2025-07-10T14:18:19Z

Hi @maass-hamburg,

All the review comments were addressed in this PR version 7. Please review and share feedback. Thanks, Vijay

Changes since v6:

- Use generic phy driver for i226. (Test Coverage: Got Satisfactory performance results)
	○ Replace the compatible string in device tree to use "ethernet-phy" generic driver.
	○ Remove drivers/ethernet/phy/phy_intel_igc.c
	○ Remove dts/bindings/ethernet/phy/intel,igc-phy.yaml
	○ Clean up drivers/ethernet/phy/CMakeLists.txt.
	○ Clean up drivers/ethernet/phy/Kconfig.

- Remove Miscellaneous interrupts handling codes from the mac driver.
	○ eth_intel_igc_misc_isr
	○ eth_intel_igc_connect_misc_msix_vector
	○ Clean eth_intel_igc_pcie_msix_setup
	○ Clean eth_intel_igc_map_intr_to_vector
	○ eth_intel_igc_intr_enable

- Remove INTEL_IGC_MAC_ASSIGN_ADDR unused macro.
- Move interrupt-parent to parent platform driver.
- Clean up the PR description.
- Fix 3 sonarqubecloud reported issues.

The Ethernet device model consists of multiple subsystem components, such as MDIO, PHY, MAC and PTP_CLOCK. These components are mapped into a single PCIe BAR location with same base address. This platform driver retrieves the MMIO mapping details and provides a framework to share it with all the child subsystem components. This approach avoid the duplicate remapping, ensures efficient re-use of MMIO mappings across related devices. Example device tree structure for first ethernet instance: parent0: parent0 { compatible = "intel,eth-plat"; interrupt-parent = <&intc>; vendor-id = <0x8086>; device-id = <0xXXXX>; igc0: igc0 { compatible = "intel,igc-mac"; /* * MAC specific properties. */ status = "okay"; }; mdio0: mdio0 { compatible = "intel,igc-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy"; /* * PHY specific properties. */ reg = <0x0>; }; }; }; This framework is modular and re-usable for other PCIe based Ethernet devices. It can also be extended to support additional platform specific information shared across child nodes. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

Intel i226 MAC supports MDIO C22 and MDIO C45. Standard PHY registers are accessible through MDIO C22, whereas PMAPMD and PCS are accssible through MDIO C45. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

Vijayakannan · 2025-07-15T04:10:00Z

Hi @maass-hamburg, please review and approve this PR.?

drivers/ethernet/intel/eth_intel_igc.c

Vijayakannan · 2025-07-16T16:03:50Z

Hi @maass-hamburg, please review PR revision v8.

Changes since PR version v7:
• Cleanup eth_intel_igc_get_phy
• Use sys_read32 and sys_write32.
• Move the intr vector configuration to normal init function.
• Cleanup eth_intel_igc_disable_pcie_master function.
• Remove unused 20millisecond sleep from eth_intel_igc_init_mac_hw.
• Add 1 millisecond delay after MAC reset sequence to settle.
• Relocate eth_intel_igc_map_intr_to_vector and eth_intel_igc_init_speed.
• Refine the inline comments and LOG prints.

drivers/ethernet/intel/eth_intel_igc.c

Vijayakannan · 2025-07-17T15:35:19Z

Hi @maass-hamburg, please review PR revision v9.

Changes since PR version v8:

Remove 0 left and right shift usages in code.
Cleanup eth_intel_igc_get_sa_family
Remove Long packet receive support. (test the speed with this support)
Cleanup INTEL_IGC_SETUP_QUEUE_WORK_EXP macro
Cleanup INTEL_IGC_MAC_DATA
Use phy-handle to fetch ethernet-phy node in dts.

The Intel i226 Ethernet Controller is a PCIe Gen 2 one-lane modular endpoint device that integrates a GbE Media Access Control (MAC) and Physical Layer (PHY) port. This driver provides support for MAC and DMA-specific initialization and runtime TX/RX operations. Key features: - MSI-X interrupts for TX/RX DMA channels. - Multiple TX/RX DMA channel support with exclusive bottom-half. - Implements a circular descriptor ring architechture with producer-consumer semantics for high performance pkt processing. - Full duplex support for 10/100/1000 Mbps. - Half duplex support for 10/100 Mbps. - Auto-negotiation for 10/100/1000 Mbps. - MTU customization for flexible packet sizes. - MAC address filtering based on: - Random MAC generation. - Local-mac-address mentioned in device tree. - EEPROM pre-programmed mac address. - Setting mac address via net shell. - Support for multiple Ethernet interface instances. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>

Foxville LM (0x125B) i226 variant and Intel Alder Lake platform was used for developing and stabilizing the i226 Ethernet device driver. However, users can reuse the provided device tree models as a reference when enabling the support for other i226 variants and platforms. This device-tree model include essential configurations for the i226 Ethernet controller, such as PCIe settings, interrupt mappings, Phy MDIO, and DMA descriptor configurations. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

The Zperf sample application was chosen to demonstrate basic network functionality and high-performance use cases. This application serves as a reference for users who wish to enable other network sample applications. In addition to the essential configurations for the Intel i226 Ethernet controller, stack-specific configurations were added to ensure stability under heavy network loads. These configurations include adjustments to buffer sizes, interrupt handling, and DMA descriptor management. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

sonarqubecloud · 2025-07-18T12:04:19Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

Vijayakannan force-pushed the dev/vijay/i226_mainline branch from f78f26a to 0e25402 Compare April 3, 2025 14:15

Vijayakannan marked this pull request as ready for review April 3, 2025 15:55

github-actions bot added area: MDIO area: Ethernet area: Networking area: Samples Samples platform: X86 x86 and x86-64 labels Apr 3, 2025

github-actions bot requested review from ceolin, dcpleung, decsny, edersondisouza, jukkar, kartben, lmajewski, maass-hamburg, najumon1980, nashif, pdgendt, ssharks, tbursztyka and teburd April 3, 2025 15:56

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Vijayakannan marked this pull request as draft April 23, 2025 05:58

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Vijayakannan added 2 commits July 11, 2025 14:18

drivers: mdio: Add Intel i226 MDIO driver support

cae6044

Intel i226 MAC supports MDIO C22 and MDIO C45. Standard PHY registers are accessible through MDIO C22, whereas PMAPMD and PCS are accssible through MDIO C45. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

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drivers: ethernet: Add Intel® i226 Ethernet Controller Driver #88108

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