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boards: tcc: topst_vcp45: add Telechips' TOPST-VCP45 board and basic device driver #83136
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Hello @pooky1004, and thank you very much for your first pull request to the Zephyr project! |
The Telechips Interrupt Controller provides hardware assistance for prioritizing | ||
and aggregating the interrupt sources for ARM Cortex-R5 processor cores. |
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help text indent it 1x tab followed by 2x spaces
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fix help text indentation in drivers/interrupt controller/Kconfig.tic file, replace 2x tabs with 1x tab followed by 2x spaces.
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void vcp_clock_init(void); | ||
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long clock_set_pll_rate(signed long id, uint32_t rate); |
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@stephanosio do we allow long types instead of int?
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change signed long and long to int32_t, unsigned long long to uint64_t, and boolean to bool.
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long clock_set_pll_rate(signed long id, uint32_t rate); | ||
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uint32_t clock_get_pll_rate(signed long id); |
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None of these are documented, doesn't look to be using the zephyr driver class properly @nordic-krch is this acceptable?
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include/zephyr/drivers/clock_control
contains vendor specific extensions to clock related features so that is ok but definitely it is missing doxygen documentation.
/* | ||
* DEFINITIONS | ||
* | ||
*/ |
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/* | |
* DEFINITIONS | |
* | |
*/ |
/* | ||
* FUNCTION PROTOTYPES | ||
* | ||
*/ |
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/* | |
* FUNCTION PROTOTYPES | |
* | |
*/ |
thee headers can go
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CONFIG_SYSCON=y | ||
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CONFIG_TIMEOUT_64BIT=y |
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soc?
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move some configs from boards/tcc/topst_vcp45/topst_vcp45_defconfig to SOC config
# Copyright 2024 Hounjoung Rim <hounjoung@tsnlab.com> | ||
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CONFIG_XIP=n | ||
CONFIG_SRAM_VECTOR_TABLE=y |
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soc?
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move some configs from boards/tcc/topst_vcp45/topst_vcp45_defconfig to SOC config
CONFIG_MAX_THREAD_BYTES=3 | ||
CONFIG_THREAD_STACK_INFO=y | ||
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CONFIG_MAX_THREAD_BYTES=3 | |
CONFIG_THREAD_STACK_INFO=y |
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change the value of CONFIG_MAX_THREAD_BYTES defined in the boards/tcc/topst_vcp45/topst_vcp45_defconfig file from 3 to 13.
/* | ||
* Copyright 2024 Hounjoung Rim <hounjoung@tsnlab.com> | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 |
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why is this needed and why can't one of the cortex_* ones in tree be used?
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Additional settings are needed for REMAP, so I use our own linker.ld file.
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Sometimes SoC's needs there own linker.ld file for various reason, and the maintainer or contributor of this should be ready to update when there are changes.
Though if the sole reason in this case is for a REMAP
memory section, then I would like to know why this memory region is not defined in devicetree and thereby become available through the use of LINKER_DT_REGIONS()
, which also exists in the cortex default linker templates.
Based on this observation, then I also doubt this SoC works with the CMake linker generator.
A basic test of this would simply be to do a build using -DCONFIG_CMAKE_LINKER_GENERATOR=y
.
(Haven't tested this PR yet)
soc/tcc/tcc7045/soc.c
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unsigned long long rem = 0; | ||
unsigned long long b = divisor; | ||
unsigned long long d = 1; | ||
unsigned long long res = 0; |
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why can't uint64 be used?
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change signed long and long to int32_t, unsigned long long to uint64_t, and boolean to bool.
soc/tcc/tcc7045/soc.h
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int32_t soc_div64_to_32(unsigned long long *pullDividend, uint32_t uiDivisor, uint32_t *puiRem); | ||
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typedef unsigned char boolean; /* for use with TRUE/FALSE */ |
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no
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change signed long and long to int32_t, unsigned long long to uint64_t, and boolean to bool.
soc/tcc/tcc7045/soc.h
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#ifndef FALSE | ||
#define FALSE (0U) | ||
#endif | ||
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#ifndef TRUE | ||
#define TRUE (1U) | ||
#endif | ||
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#ifndef NULL_PTR | ||
#define NULL_PTR ((void *)0) | ||
#endif | ||
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#ifndef NULL | ||
#define NULL (0) | ||
#endif | ||
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#ifndef ON | ||
#define ON (TRUE) | ||
#define OFF (FALSE) | ||
#endif |
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no
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I'm glad I didn't arrive too late. As for the preprocessing macros, we should align with Zephyr. Regarding the other header files, I think they also need to be updated, but I won't point them out here.
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We should now address the other maintainers' comments and get the CI back to normal.
(Maybe I missed some parts, but I need to leave it to others.)
* DEFINITIONS | ||
*/ | ||
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#define CKC_MHZ(x) (uint32_t)((x) * 1000000) |
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Please remove it, we have DT_FREQ_M
.
(or you can define an alias for it. It can be called CKC_MHZ
.)
Edit
This is just a suggestion, DT_FREQ_M
is recommended to be used in dts, but I just want to remind you.
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delete the unused CKC_MHZ(x) macro defined in the include/zephyr/drivers/clock_control/clock_control_tcc_ccu.h file.
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Add vendor-prefix tcc for vendor TELECHIPS INC., required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
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Add support for TCC7045, SoC of TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add device-tree files, required by TOPST VCP45. The device tree defines hardware details such as the CPU, timers, interrupt controller, flash memory, RAM, clock controller, UART, and GPIOs, providing a clear map of the system's architecture. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add support for TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add GPIO driver for tccvcp, required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add interrupt-controller driver for tic, required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add timer driver for tcc_vcpttc, required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add clock-control driver for tccvcp, required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add serial driver for tccvcp, required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
Add console driver for tccvcp, required by TOPST VCP45. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
add trigger_irq for topst vcp45 to subsys/test/suite/include/zephyr/interrupt util.h file. Signed-off-by: Hounjoung Rim <hounjoung@tsnlab.com>
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#include <zephyr/dt-bindings/interrupt-controller/tcc-tic.h> | ||
#include <zephyr/sys/util_macro.h> | ||
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typedef struct tic_distributor { |
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This looks awful lot like ARM GICv1, if not identical ... Any reason this cannot use the existing GIC driver?
I mean it probably is GICv1, given that the SoC is Cortex-R5.
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