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enable NETC on imx95 Cortex-A55 #571

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e44b254
fsl_common_arm: Fix comment sign issue on different architectures
Zhiqiang-Hou Jan 6, 2022
cafbc18
mcux-sdk: MIMX9596_ca55: fix A-Core header file
JiafeiPan May 29, 2025
0b84ae4
mcux-sdk: MIMX9596_ca55: disable FSL_FEATURE_NETC_HAS_ERRATA_051711
JiafeiPan May 30, 2025
b15c20f
drivers: netc: make the driver to be aarch64 compatible
JiafeiPan May 29, 2025
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10 changes: 8 additions & 2 deletions mcux/mcux-sdk-ng/drivers/common/fsl_common_arm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -474,15 +474,21 @@ _Pragma("diag_suppress=Pm120")
#endif

#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
#if defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
#define MCUX_CS "//"
#else
#define MCUX_CS "@"
#endif

/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
__attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var __attribute__((aligned(alignbytes)))
#else
#error Toolchain not supported.
#endif
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2 changes: 1 addition & 1 deletion mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c
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Expand Up @@ -129,7 +129,7 @@ status_t NETC_CmdBDRInit(netc_cbdr_hw_t *base, const netc_cmd_bdr_config_t *conf
status_t status = kStatus_Success;
uint64_t address;

if ((0U != ((uint32_t)config->bdBase % 128U)) || (0U != (config->bdLength % 8U)))
if ((0U != ((uintptr_t)config->bdBase % 128U)) || (0U != (config->bdLength % 8U)))
{
status = kStatus_InvalidArgument;
}
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2 changes: 0 additions & 2 deletions mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55.h
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Expand Up @@ -88899,7 +88899,6 @@ typedef struct {

/** ENETC_PF_TMR - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0xFC */
__I uint32_t TMR_ID; /**< Module ID, array offset: 0x0, array step: 0xFC */
uint8_t RESERVED_0[4];
__I uint32_t TMR_CAPR; /**< Timer Capability, array offset: 0x8, array step: 0xFC */
Expand Down Expand Up @@ -88940,7 +88939,6 @@ typedef struct {
__I uint32_t TMR_CUR_TIME_L; /**< Timer Current Time Low, array offset: 0xF0, array step: 0xFC */
__I uint32_t TMR_CUR_TIME_H; /**< Timer Current Time High, array offset: 0xF4, array step: 0xFC */
__IO uint32_t TMR_PARAM; /**< Timer Parameter, array offset: 0xF8, array step: 0xFC */
} ALL_REG_ARRAYS[1];
} ENETC_PF_TMR_Type;

/* ----------------------------------------------------------------------------
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2 changes: 1 addition & 1 deletion mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55_features.h
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Expand Up @@ -605,7 +605,7 @@
/* @brief After one or more late collision or excessive collision events, counters PMa_TOCTn and PMa_TFRMn will be higher than expected. */
#define FSL_FEATURE_NETC_HAS_ERRATA_051710 (1)
/* @brief MAC statistic counters TEOCT and TOCT are inaccurate after Pause frames are transmitted with flexible preamble enabled and flexible preamble count set to less than 7. */
#define FSL_FEATURE_NETC_HAS_ERRATA_051711 (1)
#define FSL_FEATURE_NETC_HAS_ERRATA_051711 (0)
/* @brief Number of Switch ports. */
#define FSL_FEATURE_NETC_SWITCH_MAX_PORT_NUMBER (5)
/* @brief Number of Switch Ethernet MAC ports. */
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