Skip to content
#

processor-design

Star

Here are 156 public repositories matching this topic...

Language: All
Filter by language
All 156 Verilog 58 SystemVerilog 26 VHDL 20 C++ 6 C 5 Python 5 Assembly 4 JavaScript 4 TeX 4 Scala 3
Sort: Most stars
Sort options
Most stars Fewest stars Most forks Fewest forks Recently updated Least recently updated

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Star 137

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design
  • Updated Jul 17, 2022
  • Verilog

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Star 137

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design
  • Updated Jul 17, 2022
  • Verilog
HaDes-V

tscheipel / HaDes-V

Star 84

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
  • Updated Jun 5, 2025
  • SystemVerilog
HaDes-V

tscheipel / HaDes-V

Star 84

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
  • Updated Jun 5, 2025
  • SystemVerilog

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

Star 17

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

computer-science processor-architecture engineering computer-engineering textbooks computer-organization computer-organisation processor-design computer-organisation-architechure computer-organization-lab computer-organization-and-design computer-organ ameythakur amey megasatish
  • Updated Mar 13, 2024
  • C

Improve this page

Add a description, image, and links to the processor-design topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the processor-design topic, visit your repo's landing page and select "manage topics."

Learn more