cpu-architecture

Here are 43 public repositories matching this topic...

arm-university / Introduction-to-Computer-Architecture-Education-Kit

Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

arm computer-engineering armv8 electrical-engineering cortex-a cpu-architecture computer-architectures hardware-design

Updated May 30, 2025
HTML

arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers

Star

A textbook on understanding system on chip design

fpga embedded-systems textbook cmsis soc fpga-soc trustzone amba cpu-architecture arm-cortex-m soc-design system-on-chip-design bus-architecture

Updated Jun 16, 2025

alirezakay / RISC-CPU

Star

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jun 19, 2021
VHDL

MaorAssayag / Architecture-of-CPU-projects

Star

VHDL , ModelSIM, Quartus, FPGA, Image Processing

fpga vhdl modelsim quartus cpu-architecture

Updated Jan 19, 2019
VHDL

dannydyl / SONY-Cell-SPU-Processor

Star

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

processor simd verilog computer-architecture vlsi cpu-architecture rtl-design dual-issue

Updated May 6, 2025
Verilog

RossComputerGuy / SherwoodArch

Sponsor

Star

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

emulator cpu virtual-machine architecture assembler computer-architecture cpu-emulator cpu-architecture sherwood-architecture

Updated Oct 29, 2018
CSS

laskarelias / upatras-riscv

Star

Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras

assembler verilog risc-v cpu-architecture bison-flex

Updated Oct 29, 2021
TeX

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Star

An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

Updated Jul 21, 2025
SystemVerilog

AkhilRai28 / ALUBuilder

Star

A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.

cpu hardware verilog alu logic-circuit arithmetic-coding digital-design cpu-architecture arithmetic-logic-unit