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dv-project

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atiqazmil / AXI4-Lite-Protocol-Checker

SystemVerilog testbench with assertions and coverage for verifying AXI4-Lite protocol compliance. Simulated using Vivado XSIM CLI with WSL2.

assertions vivado systemverilog design-verification functional-coverage axi-lite dv-project

Updated Jun 25, 2025
SystemVerilog

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