This project implements a Five-Stage Pipelining in RISC-V using a pipelined RISC-V processor with the standard five-stage pipeline:
• Instruction Fetch – Fetches the instruction from memory.
• Instruction Decode – Decodes the instruction and reads registers.
• Instruction Execution – Performs arithmetic or logical operations.
• Memory Access – Reads from or writes to memory.
• Write-Back – Writes results back to the register file.
• Definition of Pipelining:
Pipelining is a technique used in computer architecture to enhance the execution speed of instructions by overlapping multiple instruction stages. Instead of executing one instruction at a time, pipelining divides instruction execution into multiple stages, allowing multiple instructions to be processed simultaneously in different stages of execution.
Pipelined Processor:
Elaboration Design using VIVADO:
