Pinned Loading

1. 100_Days_of_Verilog 100_Days_of_Verilog Public

   Verilog 1

2. Vedic-Multiplier-using-CMOS-design Vedic-Multiplier-using-CMOS-design Public

   Transistor-level design, simulation, and layout of a 2-bit Vedic multiplier using CMOS technology with netlist and layout optimization.

3. Five_Stage_Pipelining_RISCV Five_Stage_Pipelining_RISCV Public

   Implemented a Five-Stage Pipelining in RISC-V using a pipelined RISC-V processor, incorporating the standard pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory A…

   Verilog

4. Digital-Image-Processing Digital-Image-Processing Public

   This repository contains all of my lab work for the course Digital Image Processing at IIITN.

   MATLAB 1