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1. OOO_Tomasulo_CPU OOO_Tomasulo_CPU Public

   Design a RISC-V based Out-of-Order CPU leveraging Tomasulo's Algorithm.

   SystemVerilog 1

2. fer_cgan_system fer_cgan_system Public

   Facial Expression Detection and Response System for Children

   Jupyter Notebook 1

3. hw-accel-cnns hw-accel-cnns Public

   Hardware Accelerator Design for CNNs on FPGAs

   C

4. rtl-design rtl-design Public

   RTL projects for various applications

   SystemVerilog 1

5. rtl-verif rtl-verif Public

   Projects focussing on RTL verification (UVM, SV, UVM Framework etc.,)

   SystemVerilog

6. fpga-pc-uart fpga-pc-uart Public

   Demonstrates reliable data transfer between an FPGA and a computer (PC) via UART handshake protocol

   Verilog 1