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    • CS_DAC

      Public
      A Current Steering DAC by SISLAB, VNU Information Technology Institute.
      Shell
      0000Updated Sep 23, 2025Sep 23, 2025
    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      SystemVerilog
      71001Updated Sep 12, 2025Sep 12, 2025
    • vco_adc2

      Public
      Tcl
      2000Updated Aug 15, 2025Aug 15, 2025
    • SAR-ADC

      Public
      Verilog
      2000Updated Jul 18, 2025Jul 18, 2025
    • vae_hls

      Public
      Variational AutoEncoder (VAE) with High-level Synthesis Acceleration
      C++
      0000Updated Mar 29, 2025Mar 29, 2025
    • This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      185000Updated Mar 5, 2025Mar 5, 2025
    • This is the CORE-V MCU project, hosting CORE-V's embedded-class cores with modification from SISLAB
      SystemVerilog
      65000Updated Nov 27, 2024Nov 27, 2024
    • Integration of VCO-based ADC version 2 design by SISLAB's students
      Verilog
      0000Updated Nov 24, 2024Nov 24, 2024
    • Verilog
      0000Updated Apr 1, 2024Apr 1, 2024
    • Tcl
      0000Updated Mar 18, 2024Mar 18, 2024
    • VNU-ITI SISLAB's webpage
      Ruby
      0000Updated Feb 17, 2024Feb 17, 2024
    • OpenHW Group: development platform for PlatformIO
      Python
      3000Updated Jan 5, 2023Jan 5, 2023
    • DUT

      Public
      Driver unit test
      0000Updated Dec 3, 2017Dec 3, 2017