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    24 repositories

    • Technology_Scaling-

      Public
      The TSMC Technology Scaling Reference Tool is designed to help VLSI designers, architects, and engineers make informed decisions about technology node migration and early-stage design planning. This tool provides verified scaling data for TSMC processes from 180nm to 2nm, helping you understand the trade-offs between different technology nodes.
      2•0•0•0•Updated Sep 1, 2025Sep 1, 2025

    • jtag_avip

      Public
      SystemVerilog
      •2•0•0•0•Updated Jul 4, 2025Jul 4, 2025

    • ahb_avip

      Public
      SystemVerilog
      •4•0•1•0•Updated Jun 24, 2025Jun 24, 2025

    • i2s_avip

      Public
      SystemVerilog
      •5•0•0•0•Updated Jun 17, 2025Jun 17, 2025

    • uart_avip

      Public
      JavaScript
      •2•0•0•0•Updated Jun 5, 2025Jun 5, 2025

    • spi_avip

      Public
      SystemVerilog
      •
      MIT License
      •7•9•0•0•Updated Jun 3, 2025Jun 3, 2025

    • axi4_avip

      Public
      SystemVerilog
      •
      MIT License
      •32•36•42•1•Updated Jun 3, 2025Jun 3, 2025

    • apb_avip

      Public
      SystemVerilog
      •
      MIT License
      •14•16•0•0•Updated Jun 2, 2025Jun 2, 2025

    • axi4Lite_avip

      Public
      This project deals with the axi4Lite protocol
      SystemVerilog
      •2•7•6•0•Updated Jun 2, 2025Jun 2, 2025

    • architecture-course-labs

      Public
      These are the labs that we use for the architecture training at Mirafra.
      Verilog
      •1•0•0•0•Updated Apr 23, 2025Apr 23, 2025

    • spisimulator

      Public
      This is the code for MIPS instruction set simulator from https://sourceforge.net/projects/spimsimulator.
      C++
      •0•0•0•0•Updated Apr 2, 2025Apr 2, 2025

    • i3c_avip

      Public
      Verification IP project for I3C protocol
      SystemVerilog
      •8•19•3•0•Updated Mar 8, 2025Mar 8, 2025

    • SystemVerilogCourse

      Public
      This is a detailed SystemVerilog course
      SystemVerilog
      •51•116•0•0•Updated Mar 4, 2025Mar 4, 2025

    • digitalDesignCourse

      Public
      Structured and peer-reviewed course for Digital Design Systems
      Verilog
      •
      MIT License
      •4•5•0•0•Updated May 31, 2024May 31, 2024

    • pulpino__i2c_master__ip_verification

      Public
      IP Veriification of I2C master using the I3C VIP
      SystemVerilog
      •2•4•1•0•Updated May 29, 2024May 29, 2024

    • neovim

      Public
      This project is created to arrange and align different nvim editor plugins to make the DesignVerification tasks faster.
      Lua
      •
      MIT License
      •0•1•3•0•Updated Feb 20, 2024Feb 20, 2024

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •699•0•0•0•Updated Feb 11, 2024Feb 11, 2024

    • cpu-lite

      Public
      CPU Lite is a small CPU designed for instruction purposes.
      Python
      •2•3•0•0•Updated Feb 11, 2024Feb 11, 2024

    • UVMCourse

      Public
      Structured UVM Course
      SystemVerilog
      •17•47•0•0•Updated Jan 4, 2024Jan 4, 2024

    • svunit

      Public
      SystemVerilog
      •
      Apache License 2.0
      •65•1•0•0•Updated Dec 14, 2023Dec 14, 2023

    • mbits-mirafra.github.io

      Public
      Website for mbits
      JavaScript
      •
      MIT License
      •1•2•0•0•Updated Oct 20, 2022Oct 20, 2022

    • .github

      Public
      MIT License
      •0•0•0•0•Updated Sep 14, 2022Sep 14, 2022

    • pulpino__spi_master__subsystem_verification

      Public
      SystemVerilog
      •
      MIT License
      •5•9•0•0•Updated Sep 14, 2022Sep 14, 2022

    • pulpino__spi_master__ip_verification

      Public
      SystemVerilog
      •
      MIT License
      •4•6•0•0•Updated Sep 14, 2022Sep 14, 2022