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    • Fault injection tool for reliability assessment of deep learning algorithm such as Neural Networks
      Python
      2000Updated Jul 4, 2025Jul 4, 2025
    • A development environment for RISCV ISA
      Makefile
      0000Updated Jun 10, 2025Jun 10, 2025
    • fod

      Public
      Jupyter Notebook
      0000Updated Jun 3, 2025Jun 3, 2025
    • I99T

      Public
      ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
      VHDL
      175800Updated May 14, 2025May 14, 2025
    • This repository is a comprehensive collection of benchmarks for Deep Neural Networks (DNNs), designed to evaluate and compare the performance of various models across different hardware configurations, frameworks, and datasets.
      Python
      0200Updated Apr 29, 2025Apr 29, 2025
    • byron

      Public
      An evolutionary source-code fuzzer
      Jupyter Notebook
      11206Updated Apr 19, 2025Apr 19, 2025
    • testcrush

      Public
      A Software Test Library compaction tool based on VC-Z01X.
      Python
      2201Updated Apr 3, 2025Apr 3, 2025
    • RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione
      Python
      21411Updated Oct 22, 2024Oct 22, 2024
    • Stuck-At Software Test Libraries for the pulpino-ri5cy SoC
      Assembly
      0400Updated May 29, 2024May 29, 2024
    • r4ves

      Public
      RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
      Verilog
      1100Updated May 28, 2024May 28, 2024
    • Python
      1000Updated Apr 26, 2024Apr 26, 2024
    • X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK) with Tensorflow Lite for Microcontrollers support.
      C
      10000Updated Apr 26, 2024Apr 26, 2024
    • C++
      1000Updated Mar 2, 2024Mar 2, 2024
    • .github

      Public
      0000Updated Feb 26, 2024Feb 26, 2024
    • CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      465100Updated Jan 28, 2024Jan 28, 2024
    • IPApproX

      Public
      Set of IP management tools used within the context of the PULP project
      Python
      25000Updated Jul 26, 2023Jul 26, 2023
    • SBST/FuSa environment for Pulpino - An open-source microcontroller system based on RISC-V
      C
      313000Updated Jul 26, 2023Jul 26, 2023
    • howto

      Public
      A collection of howto guides
      0000Updated Jul 16, 2023Jul 16, 2023
    • fenice

      Public
      Customizable fault-simulation and gate-level editing library for sequential circuits
      C
      1700Updated Apr 20, 2021Apr 20, 2021