A development environment for RISCV ISA. Made for running simulation using two key tools: spike and Verilator (with core-v-verify). The main target is Software Test Libraries (STLs), and with this environment you can either emulate the execution of RISC-V programs in software, making it ideal for bare-metal software development, or simulate and validate RISC-V cores at the RTL (Register Transfer Level) with core-v-verify that include SystemVerilog testbenches made to simulate an actual RISC-V processor such as CV32E40P.
The spike simulation can be launched from the makefile typing $ make GOAL=spike, in this way the default test (swhw1) will be run. To run a specific test the syntax is $ make GOAL=spike TEST=test_name where test_name is the name of the directory where the .c and .S are stored.
After the execution all the generated files will be placed in a directory named spike_results:
e.g.
spike_results/
└── swhw1
├── objects
│ └── swhw.o
└── swhw1_spike
where swhw1_spike is the executable
If you want to clean all the files and folders generated by a spike simulation ($ make GOAL=spike ...) you have to use $ make clean-spike and all the files in spike_results will be trashed. Whereas if you want to clean only the files (object and executable) of a specific test run: $ make clean-spike-test TEST='test_name'.
The Verilator simulation can be launched from the makefile typing $ make GOAL=verilator, even though the GOAL can be omitted since verilator is the default, in this way the default test (swhw1) will be run. To run a specific test the syntax is $ make GOAL=verilator TEST=test_name where test_name is the name of the directory where the .c and .S are stored.
After the execution all the generated file will be placed in a directory named simulation_result:
e.g
simulation_results/
└── swhw1
├── 0
│ └── test_program
│ ├── bsp
│ │ ├── crt0.o
│ │ ├── handlers.o
│ │ ├── libcv-verif.a
│ │ ├── Makefile
│ │ ├── syscalls.o
│ │ └── vectors.o
│ └── swhw1.log
└── verilator_executable
where verilator_executable is the executable.
another directory created is cobj_result: the directory where it's stored the core testbench generated by the first run of the Makefile.
To allow the creation of the vcd file as you run the test add in the make $ ... WAVES=1. The vcd will be created as verilator_tb.vcd and will appear in the current folder.
If you want to clean all the file generated for verilator by the $ make ..., including all the tb, you have to type $ make clean, with this all the .hex .elf ..., all the tb contained in cobj_dir and the simulation_results folder will be cleared.
All the tests are stored in the programs directory. To add a new test you can create a new directory and add all the .S files with the .c, then put a file test.yaml containing name: "testname"
uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c #TODO: risolvere il problema di avere test.yaml
description: >
"testname" sanity test
once all of this is implemented the test can be executed.
If you want to use the pulpino STLs copy the test in programs and add the yaml.
Install the environment typing in the shell:
$ git clone https://github.com/cad-polito-it/RISCV-CAD-IDE.git
To work, the environment need: core-v-verify, RISC-V toolchain, spike, Verilator and the proxy kernel.
All the repository should be already cloned into the main one but to complete all the installations follow the instruction given by the developers:
- RISC-V toolchain (riscv-gnu-toolchain) N.B. make sure to follow the 32-bit toolchain
- spike (riscv-isa-sim)
- proxy kernel (riscv-pk)
- verilator
- core-v-verify
Some variables must be changed after the installation of the dependencies:
In the yaml2make located in core-v-verif/bin put your programs absolute or relative path starting from the core-v-verif, e.g. ../programs (relative) /home/usr/programs (absolute)
To make it work there are some variables that must be defined. To do that you have to run $ source ./setup.sh in the shell.
Make sure to change the variable if needed:
- riscv toolchain, this isn't defined in the Makefile and should be defined as CV_SW_TOOLCHAIN with an export, e.g /home/usr/opt/riscv;
- toolchain prefix, this isn't defined in the Makefile and should be defined as CV_SW_PREFIX with an export, e.g riscv64-unknown-elf-;
- compiler, this isn't defined in the Makefile and should be defined as CV_SW_CC with an export, e.g gcc;
- configuration, the default definition and export is rv32imc_zicsr, but it can be changed;
- Gabriele Belli
- Francesco Angione
- Riccardo Cantoro