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[AMDGPU][NPM] Add isRequired to passes missing it #148115

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1 change: 1 addition & 0 deletions llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin<StructurizeCFGPass> {
function_ref<StringRef(StringRef)> MapClassName2PassName);

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/include/llvm/Transforms/Utils/LoopSimplify.h
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ class ScalarEvolution;
class LoopSimplifyPass : public PassInfoMixin<LoopSimplifyPass> {
public:
LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
static bool isRequired() { return true; }
};

/// Simplify each loop in a loop nest recursively.
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPU.h
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
SILowerI1CopiesPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};

void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
Expand Down Expand Up @@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
public:
SIModeRegisterPass() {}
PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
static bool isRequired() { return true; }
};

class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
Expand Down Expand Up @@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass
public:
SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
static bool isRequired() { return true; }
};

void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
Original file line number Diff line number Diff line change
Expand Up @@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {

PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};

class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass
: public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
public:
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
static bool isRequired() { return true; }
};

} // end namespace llvm
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/GCNNSAReassign.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin<GCNNSAReassignPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ class GCNPreRALongBranchRegPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ class GCNRewritePartialRegUsesPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ class SIFixSGPRCopiesPass : public PassInfoMixin<SIFixSGPRCopiesPass> {
SIFixSGPRCopiesPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};

} // namespace llvm
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ class SIFixVGPRCopiesPass : public PassInfoMixin<SIFixVGPRCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SILowerControlFlow.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ class SILowerControlFlowPass : public PassInfoMixin<SILowerControlFlowPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ class SILowerSGPRSpillsPass : public PassInfoMixin<SILowerSGPRSpillsPass> {
// SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
return MachineFunctionProperties().setIsSSA().setNoVRegs();
}
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ class SILowerWWMCopiesPass : public PassInfoMixin<SILowerWWMCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ class SIPreAllocateWWMRegsPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};

} // namespace llvm
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ class SIWholeQuadModePass : public PassInfoMixin<SIWholeQuadModePass> {
MachineFunctionProperties getClearedProperties() const {
return MachineFunctionProperties().setIsSSA();
}
static bool isRequired() { return true; }
};
} // namespace llvm

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1 change: 0 additions & 1 deletion llvm/test/Feature/optnone-opt.ll
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,6 @@ attributes #0 = { optnone noinline }
; Loop IR passes that opt doesn't turn on by default.
; LoopPassManager should not be skipped over an optnone function
; NPM-LOOP-NOT: Skipping pass: PassManager
; NPM-LOOP-DAG: Skipping pass: LoopSimplifyPass on foo
; NPM-LOOP-DAG: Skipping pass: LCSSAPass
; NPM-LOOP-DAG: Skipping pass: IndVarSimplifyPass
; NPM-LOOP-DAG: Skipping pass: SimpleLoopUnswitchPass
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