[AMDGPU][NPM] Add isRequired to passes missing it #148115
Open
+17
−1
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This was referenced Jul 11, 2025
|
Warning This pull request is not mergeable via GitHub because a downstack PR is open. Once all requirements are satisfied, merge this PR as a stack on Graphite.
This stack of pull requests is managed by Graphite. Learn more about stacking. |
|
@llvm/pr-subscribers-backend-amdgpu Author: Vikram Hegde (vikramRH) Changessame as #134033. adds StructurizeCFG and LoopSimplify to the list. originally authored by @optimisan Full diff: https://github.com/llvm/llvm-project/pull/148115.diff 16 Files Affected:
diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
index f68067d935458..f50511c9c0972 100644
--- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
+++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
@@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin<StructurizeCFGPass> {
function_ref<StringRef(StringRef)> MapClassName2PassName);
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
index 8f3fa1f2b18ef..d179002fd6a27 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
@@ -54,6 +54,7 @@ class ScalarEvolution;
class LoopSimplifyPass : public PassInfoMixin<LoopSimplifyPass> {
public:
LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
/// Simplify each loop in a loop nest recursively.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 23f106a9c1d4d..4a19fe3df6fd9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
SILowerI1CopiesPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
@@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
public:
SIModeRegisterPass() {}
PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
@@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass
public:
SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index f3b9364fdb92b..db5a1c0ac71aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
index 2fd98a2ee1a93..d6fb0e53e1169 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
@@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass
: public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
public:
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
index 97a72e7ddbb24..4f2abe0dd0086 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
@@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin<GCNNSAReassignPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
index 4cd7dea83a061..4c4ac344cb206 100644
--- a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
+++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
@@ -17,6 +17,7 @@ class GCNPreRALongBranchRegPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
index b2c3190b5c6ba..4e97128bdc2d5 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
@@ -17,6 +17,7 @@ class GCNRewritePartialRegUsesPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
index d7551a45887b9..12b87d756e664 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
@@ -18,6 +18,7 @@ class SIFixSGPRCopiesPass : public PassInfoMixin<SIFixSGPRCopiesPass> {
SIFixSGPRCopiesPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
index 7b098b71597ff..0637b5d1750f9 100644
--- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
+++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
@@ -16,6 +16,7 @@ class SIFixVGPRCopiesPass : public PassInfoMixin<SIFixVGPRCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
index 23803c679c246..478558dfbf97f 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
@@ -16,6 +16,7 @@ class SILowerControlFlowPass : public PassInfoMixin<SILowerControlFlowPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
index 64ba3029f1c55..cfc25bba764e9 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
@@ -21,6 +21,7 @@ class SILowerSGPRSpillsPass : public PassInfoMixin<SILowerSGPRSpillsPass> {
// SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
return MachineFunctionProperties().setIsSSA().setNoVRegs();
}
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
index cfc8100901760..5c17a479d953c 100644
--- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
+++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
@@ -16,6 +16,7 @@ class SILowerWWMCopiesPass : public PassInfoMixin<SILowerWWMCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
index 9964817649168..6eae4756d59b2 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
@@ -18,6 +18,7 @@ class SIPreAllocateWWMRegsPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
index 87350b810bba7..b49a0fc3f6a4d 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
@@ -20,6 +20,7 @@ class SIWholeQuadModePass : public PassInfoMixin<SIWholeQuadModePass> {
MachineFunctionProperties getClearedProperties() const {
return MachineFunctionProperties().setIsSSA();
}
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/test/Feature/optnone-opt.ll b/llvm/test/Feature/optnone-opt.ll
index 83ff946320f53..795c9bd544463 100644
--- a/llvm/test/Feature/optnone-opt.ll
+++ b/llvm/test/Feature/optnone-opt.ll
@@ -54,7 +54,6 @@ attributes #0 = { optnone noinline }
; Loop IR passes that opt doesn't turn on by default.
; LoopPassManager should not be skipped over an optnone function
; NPM-LOOP-NOT: Skipping pass: PassManager
-; NPM-LOOP-DAG: Skipping pass: LoopSimplifyPass on foo
; NPM-LOOP-DAG: Skipping pass: LCSSAPass
; NPM-LOOP-DAG: Skipping pass: IndVarSimplifyPass
; NPM-LOOP-DAG: Skipping pass: SimpleLoopUnswitchPass
|
|
@llvm/pr-subscribers-llvm-transforms Author: Vikram Hegde (vikramRH) Changessame as #134033. adds StructurizeCFG and LoopSimplify to the list. originally authored by @optimisan Full diff: https://github.com/llvm/llvm-project/pull/148115.diff 16 Files Affected:
diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
index f68067d935458..f50511c9c0972 100644
--- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
+++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
@@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin<StructurizeCFGPass> {
function_ref<StringRef(StringRef)> MapClassName2PassName);
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
index 8f3fa1f2b18ef..d179002fd6a27 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
@@ -54,6 +54,7 @@ class ScalarEvolution;
class LoopSimplifyPass : public PassInfoMixin<LoopSimplifyPass> {
public:
LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
/// Simplify each loop in a loop nest recursively.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 23f106a9c1d4d..4a19fe3df6fd9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
SILowerI1CopiesPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
@@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
public:
SIModeRegisterPass() {}
PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
@@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass
public:
SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index f3b9364fdb92b..db5a1c0ac71aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
index 2fd98a2ee1a93..d6fb0e53e1169 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
@@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass
: public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
public:
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+ static bool isRequired() { return true; }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
index 97a72e7ddbb24..4f2abe0dd0086 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
@@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin<GCNNSAReassignPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
index 4cd7dea83a061..4c4ac344cb206 100644
--- a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
+++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
@@ -17,6 +17,7 @@ class GCNPreRALongBranchRegPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
index b2c3190b5c6ba..4e97128bdc2d5 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
@@ -17,6 +17,7 @@ class GCNRewritePartialRegUsesPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
index d7551a45887b9..12b87d756e664 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
@@ -18,6 +18,7 @@ class SIFixSGPRCopiesPass : public PassInfoMixin<SIFixSGPRCopiesPass> {
SIFixSGPRCopiesPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
index 7b098b71597ff..0637b5d1750f9 100644
--- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
+++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
@@ -16,6 +16,7 @@ class SIFixVGPRCopiesPass : public PassInfoMixin<SIFixVGPRCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
index 23803c679c246..478558dfbf97f 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
@@ -16,6 +16,7 @@ class SILowerControlFlowPass : public PassInfoMixin<SILowerControlFlowPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
index 64ba3029f1c55..cfc25bba764e9 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
@@ -21,6 +21,7 @@ class SILowerSGPRSpillsPass : public PassInfoMixin<SILowerSGPRSpillsPass> {
// SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
return MachineFunctionProperties().setIsSSA().setNoVRegs();
}
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
index cfc8100901760..5c17a479d953c 100644
--- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
+++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
@@ -16,6 +16,7 @@ class SILowerWWMCopiesPass : public PassInfoMixin<SILowerWWMCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
index 9964817649168..6eae4756d59b2 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
@@ -18,6 +18,7 @@ class SIPreAllocateWWMRegsPass
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
index 87350b810bba7..b49a0fc3f6a4d 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
@@ -20,6 +20,7 @@ class SIWholeQuadModePass : public PassInfoMixin<SIWholeQuadModePass> {
MachineFunctionProperties getClearedProperties() const {
return MachineFunctionProperties().setIsSSA();
}
+ static bool isRequired() { return true; }
};
} // namespace llvm
diff --git a/llvm/test/Feature/optnone-opt.ll b/llvm/test/Feature/optnone-opt.ll
index 83ff946320f53..795c9bd544463 100644
--- a/llvm/test/Feature/optnone-opt.ll
+++ b/llvm/test/Feature/optnone-opt.ll
@@ -54,7 +54,6 @@ attributes #0 = { optnone noinline }
; Loop IR passes that opt doesn't turn on by default.
; LoopPassManager should not be skipped over an optnone function
; NPM-LOOP-NOT: Skipping pass: PassManager
-; NPM-LOOP-DAG: Skipping pass: LoopSimplifyPass on foo
; NPM-LOOP-DAG: Skipping pass: LCSSAPass
; NPM-LOOP-DAG: Skipping pass: IndVarSimplifyPass
; NPM-LOOP-DAG: Skipping pass: SimpleLoopUnswitchPass
|
|
Should use the |
arsenm
approved these changes
Jul 11, 2025
cdevadas
approved these changes
Jul 11, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
same as #134033. adds StructurizeCFG and LoopSimplify to the list.
The skipFunction check is done automatically in OptNone instrumentation, we have to add this method to passes that should not be skipped
Co-authored-by : Oke, Akshat <Akshat.Oke@amd.com>