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[LegalizeTypes] Preserve disjoint flag when expanding OR. #147640

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Merged
merged 5 commits into from
Jul 9, 2025
Merged

[LegalizeTypes] Preserve disjoint flag when expanding OR. #147640

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70af45d
Pre-commit tests.
topperc Jul 9, 2025
7c17a53
[RISCV] Select disjoint_or+not as xnor.
topperc Jul 9, 2025
727e78c
fixup! Rename or_is_add to or_disjoint to better reflect new usage.
topperc Jul 9, 2025
98cfe7a
[LegalizeTypes] Preserve disjoint flag when expanding OR.
topperc Jul 9, 2025
e968b1c
Merge remote-tracking branch 'origin/main' into pr/disjoint-xor-2
topperc Jul 9, 2025
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9 changes: 7 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4380,8 +4380,13 @@ void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
SDValue LL, LH, RL, RH;
GetExpandedInteger(N->getOperand(0), LL, LH);
GetExpandedInteger(N->getOperand(1), RL, RH);
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);

SDNodeFlags Flags;
if (N->getOpcode() == ISD::OR)
Flags.setDisjoint(N->getFlags().hasDisjoint());
Comment on lines +4384 to +4386
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Isn't this the same as just directly using the original value of N->getFlags

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It is now, but it could be wrong if a new flag is added in the future that can't be preserved.


Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL, Flags);
Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH, Flags);
}

void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Expand Up @@ -3441,7 +3441,7 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
return false;
}

bool RISCVDAGToDAGISel::orIsAdd(const SDNode *N) const {
bool RISCVDAGToDAGISel::orDisjoint(const SDNode *N) const {
if (N->getFlags().hasDisjoint())
return true;
KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
Expand Down Expand Up @@ -3474,7 +3474,7 @@ bool RISCVDAGToDAGISel::selectZExtImm32(SDValue N, SDValue &Val) {
case ISD::ADD:
break;
case ISD::OR:
if (orIsAdd(U))
if (orDisjoint(U))
break;
return false;
default:
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
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Expand Up @@ -125,7 +125,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool selectNegImm(SDValue N, SDValue &Val);
bool selectInvLogicImm(SDValue N, SDValue &Val);

bool orIsAdd(const SDNode *Node) const;
bool orDisjoint(const SDNode *Node) const;
bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
const unsigned Depth = 0) const;
bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 8); }
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14 changes: 9 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -1450,15 +1450,19 @@ def : PatGprUimmLog2XLen<sra, SRAI>;

// Select 'or' as ADDI if the immediate bits are known to be 0 in $rs1. This
// can improve compressibility.
def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
return orIsAdd(N);
def riscv_or_disjoint : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
return orDisjoint(N);
}]>;
def : PatGprSimm12<or_is_add, ADDI>;
def : PatGprSimm12<riscv_or_disjoint, ADDI>;

def add_like : PatFrags<(ops node:$lhs, node:$rhs),
[(or_is_add node:$lhs, node:$rhs),
[(riscv_or_disjoint node:$lhs, node:$rhs),
(add node:$lhs, node:$rhs)]>;

def riscv_xor_like : PatFrags<(ops node:$lhs, node:$rhs),
[(riscv_or_disjoint node:$lhs, node:$rhs),
(xor node:$lhs, node:$rhs)]>;

// negate of low bit can be done via two (compressible) shifts. The negate
// is never compressible since rs1 and rd can't be the same register.
def : Pat<(i32 (sub 0, (and_oneuse GPR:$rs, 1))),
Expand Down Expand Up @@ -2160,7 +2164,7 @@ def : PatGprImm<binop_allwusers<xor>, XORI, u32simm12>;
// Select 'or' as ADDIW if the immediate bits are known to be 0 in $rs1 and
// $rs1 is sign extended. This can improve compressibility. Using ADDIW gives
// more power to RISCVOptWInstrs.
def : Pat<(or_is_add 33signbits_node:$rs1, simm12:$imm),
def : Pat<(riscv_or_disjoint 33signbits_node:$rs1, simm12:$imm),
(ADDIW $rs1, simm12:$imm)>;

/// Loads
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Expand Up @@ -931,11 +931,11 @@ multiclass VPatWidenOrDisjoint_VV_VX<SDNode extop, string instruction_name> {
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(wti.Vector (extop (vti.Vector (or_is_add vti.RegClass:$rs2, vti.RegClass:$rs1)))),
def : Pat<(wti.Vector (extop (vti.Vector (riscv_or_disjoint vti.RegClass:$rs2, vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(wti.Vector (extop (vti.Vector (or_is_add vti.RegClass:$rs2, (SplatPat (XLenVT GPR:$rs1)))))),
def : Pat<(wti.Vector (extop (vti.Vector (riscv_or_disjoint vti.RegClass:$rs2, (SplatPat (XLenVT GPR:$rs1)))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
GPR:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Expand Up @@ -653,7 +653,7 @@ let HasOneUse = 1 in {
node:$E),
(riscv_or_vl node:$A, node:$B, node:$C,
node:$D, node:$E), [{
return orIsAdd(N);
return orDisjoint(N);
}]>;
def riscv_sub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
node:$E),
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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Expand Up @@ -497,7 +497,8 @@ def invLogicImm : ComplexPattern<XLenVT, 1, "selectInvLogicImm", [], [], 0>;
let Predicates = [HasStdExtZbbOrZbkb] in {
def : Pat<(XLenVT (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
def : Pat<(XLenVT (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
def : Pat<(XLenVT (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
def : Pat<(XLenVT (not (riscv_xor_like GPR:$rs1, GPR:$rs2))),
(XNOR GPR:$rs1, GPR:$rs2)>;

def : Pat<(XLenVT (and GPR:$rs1, invLogicImm:$rs2)), (ANDN GPR:$rs1, invLogicImm:$rs2)>;
def : Pat<(XLenVT (or GPR:$rs1, invLogicImm:$rs2)), (ORN GPR:$rs1, invLogicImm:$rs2)>;
Expand Down
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