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[LegalizeTypes] Preserve disjoint flag when expanding OR. #147640

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[LegalizeTypes] Preserve disjoint flag when expanding OR. #147640

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70af45d
Pre-commit tests.
topperc Jul 9, 2025
7c17a53
[RISCV] Select disjoint_or+not as xnor.
topperc Jul 9, 2025
727e78c
fixup! Rename or_is_add to or_disjoint to better reflect new usage.
topperc Jul 9, 2025
98cfe7a
[LegalizeTypes] Preserve disjoint flag when expanding OR.
topperc Jul 9, 2025
e968b1c
Merge remote-tracking branch 'origin/main' into pr/disjoint-xor-2
topperc Jul 9, 2025
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9 changes: 7 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4380,8 +4380,13 @@ void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
SDValue LL, LH, RL, RH;
GetExpandedInteger(N->getOperand(0), LL, LH);
GetExpandedInteger(N->getOperand(1), RL, RH);
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);

SDNodeFlags Flags;
if (N->getOpcode() == ISD::OR)
Flags.setDisjoint(N->getFlags().hasDisjoint());
Comment on lines +4384 to +4386
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Isn't this the same as just directly using the original value of N->getFlags

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It is now, but it could be wrong if a new flag is added in the future that can't be preserved.


Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL, Flags);
Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH, Flags);
}

void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
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20 changes: 13 additions & 7 deletions llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
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Expand Up @@ -128,13 +128,19 @@ define i32 @disjoint_or_xnor_i32(i32 %a, i32 %b) nounwind {
}

define i64 @disjoint_or_xnor_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: disjoint_or_xnor_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: or a1, a1, a3
; CHECK-NEXT: or a0, a0, a2
; CHECK-NEXT: not a0, a0
; CHECK-NEXT: not a1, a1
; CHECK-NEXT: ret
; RV32I-LABEL: disjoint_or_xnor_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: ret
;
; RV32ZBB-ZBKB-LABEL: disjoint_or_xnor_i64:
; RV32ZBB-ZBKB: # %bb.0:
; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a2
; RV32ZBB-ZBKB-NEXT: xnor a1, a1, a3
; RV32ZBB-ZBKB-NEXT: ret
%or = or disjoint i64 %a, %b
%not = xor i64 %or, -1
ret i64 %not
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