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possible bug in pclib/ifcs/ValRdyBundle.py

Status: Open.

#183 In cornell-brg/pymtl;

· 3gx opened on Oct 25, 2019

Slice on fields in bitstruct does not produce valid Verilog

Status: Open.

#179 In cornell-brg/pymtl;

· wizard97 opened on Feb 11, 2019

sext(concat()) does not translate

Status: Open.

#178 In cornell-brg/pymtl;

· wizard97 opened on Feb 11, 2019

Python list slicing translation

Status: Open.

#177 In cornell-brg/pymtl;

· wizard97 opened on Jan 28, 2019

Help with design low-level HDL language

Status: Open.

#171 In cornell-brg/pymtl;

· XVilka opened on Nov 16, 2018

Is it possible to generate sequential blocks in runtime?

Status: Open.

#169 In cornell-brg/pymtl;

· zhuanhao-wu opened on Oct 26, 2018

will pymtl be ported to Python3

Status: Open.

#167 In cornell-brg/pymtl;

· CFAndy opened on Sep 14, 2018

pymtl does check ".value" for single level Wire/OutPort but doesn't for the second level within message type

Status: Open.

#162 In cornell-brg/pymtl;

· jsn1993 opened on Oct 20, 2016

The order of test matters. I think this is a bug

Status: Open.

#157 In cornell-brg/pymtl;

· jsn1993 opened on Aug 25, 2016

explicit_modulename doesn't work for a very simple verilog import

Status: Open.

#153 In cornell-brg/pymtl;

· jsn1993 opened on Jul 20, 2016

Verilog translation

Bits

verilog_translation

wontfix

Status: Open.

#147 In cornell-brg/pymtl;

· Abhinav117 opened on Mar 5, 2016

connecting wire slice to wire slice seems not to work

Status: Open.

#144 In cornell-brg/pymtl;

· cbatten opened on Oct 30, 2015