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Is it possible to generate sequential blocks in runtime? #169

@zhuanhao-wu

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@zhuanhao-wu

If I want to:

  1. generate a state-machine dynamically based on the user input of states and transitions,
  2. then translate the module into Verilog,

is there an easy way to accomplish this?

I have tried generating the AST / the string of the sequential block function, but the Verilog translator requires source code of the block, which is inaccessible.

I could also try writing a template python file and fill in the state transitions and wire declarations but this does not seem natural to me.

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