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Configure everything via YAML

Status: Open.

#9 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on May 29, 2024

Remake pointer and config Python scripts

Status: Open.

#8 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Apr 3, 2024

Make sure config registers can be read back

Status: Open.

#7 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Apr 3, 2024

Make sure pointers are always on 0xFF

Status: Open.

#6 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Apr 3, 2024

Add complete SPI interface generation module and Python code

Status: Open.

#5 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Feb 26, 2024

Add SRAM power down module (currently ready in work machine)

Status: Open.

#4 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Feb 24, 2024

Add SPI tests (SystemVerilog scripts currently ready in work machine)

Status: Open.

#3 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Feb 24, 2024

Create script to generate full SPI interface (including memory managers and configuration memory

Status: Open.

#1 In cogsys-tudelft/asic-cells;

· V0XNIHILI opened on Jan 30, 2024