This library has been developed by the Cognitive Sensor Nodes and Systems lab at Delft University of Technology.
This repository contains a set of (System)Verilog modules that can be used in ASIC design and FPGA prototyping. Tests for these modules are also provided and created using cocotb.
Simply clone the repository and use bender update to install all dependencies.
To install the basic driver and hardware generation code, use:
pip install .
To also install the dependencies for the tests, use:
pip install . [test]
The Verilog modules are divided into the following categories:
Two modules are present for AER communication: high_speed_in_bus and high_speed_out_bus. These modules are used to communicate with a chip that uses AER communication. The modules are based on the AER protocol for spiking neural networks.
The in-bus handles the incoming and outgoing request and acknowledge signals, while the out-bus handles the sending of (multiple) output data.
The clock directory contains a clock divider (clock_divider, number of stages can be specified via a parameter) which consists of multiple frequency_divider_stage modules. It also has a simple OR gate (ext_or_int_clock) that switches between an external and internal clock to make SDC constraint definitions easier.
Two domain crossing modules are provided: a double_flop_synchronizer and a triple_flop_synchronizer. For the triple flop synchronizer, there is also a variant where the output goes high if the input toggles: triple_flop_toggle_synchronizer, while also a wide (multi-bit) version of the double flop synchronizer is provided: wide_double_flop_synchronizer. All of these modules can be used to cross from a slow clock domain (input data) to a fast clock domain. For more information about clock domain crossing see here for information about a double flop synchronizer and here for information about clock domain crossing in general.
The SPI interface provided in this repository offers the following features:
- Writing to a set of SPI-addressable configuration registers
- Reading from a set of SPI-addressable on-chip registers
- Reading/writing to/from a set of SPI-addressable on-chip memories
The full SPI interface is parametrizable; the main ASIC-side interface can be found in spi_client. For writing to a set of addressable configuration registers, for example for controlling the operation of your ASIC, use the generate_config_memory.py script to generate the Verilog code for the configuration memory. Similarly, for reading from on-chip registers, generate_pointers.py can be used to generate the Verilog code for the pointer memory (with pointers values on-chip that can be accessed via an address over SPI are indicated). Finally, a memory_manager module is provided that can be used to read/write to/from on-chip memories: this module should be used in conjunction with the spi_clock_barrier_crossing module to cross from the SPI clock domain to the ASIC clock domain while communicating data with the SRAMs.
Two parametrizable SRAM modules are provided: a single port memory with write mask (single_port_type_t_sram.sv) and a dual port memory (dual_port_type_t_sram.sv) with write mask. Note that the dual port memory supports one read and write in parallel, but not two writes or two reads in parallel.